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tulip

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mismatch problem for carefully layouted circuit
Jan 21^st, 2014, 1:03am

If I carefully layout the circuit, for example, some reused identical cells are placed in a line and in minimum distance.
1.Does the mismatch parameters be much smaller than the parameters provided by the foundry?
2. If it is the case, can I predict the new MC parameters?
3. Are there some cases that with perfect layout, the mismatch can be ignored?

Thank you

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boe Community Fellow Offline Posts: 615	Re: mismatch problem for carefully layouted circuit Reply #1 - Jan 21^st, 2014, 3:31am Hi tulip, I obviously don't know what your FAB did w.r.t. MC modeling, but generally mismatch parameters are for a good layout and you should expect worse matching than given by MC parameters if you do not follow good layout practices. - B O E
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Tiger9999

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Re: mismatch problem for carefully layouted circuit
Reply #2 - Jan 22^nd, 2014, 5:59am

Hi~
The mismatch report given by the foundry is tested under the conditions they assumed but no care for layout techniques. Applying matching layout techniques improves devices matching. Do not confuse or obstacle yourself when deign circuit. Mismatch report is a kind of guideline or reference when your design or layout without applying matching techniques.

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RobG

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Bozeman, MT

Re: mismatch problem for carefully layouted circuit
Reply #3 - Jan 22^nd, 2014, 8:46am

I agree with Boe and Tiger9999, even though they are opposite opinions Wink

. In general layout asymmetries doesn't affect the spread (standard deviation) of a mismatch. Instead it creates a systematic error, that is, it affects the average (mean) offset. At least that is true in the older processes.

For example, an opamp with good layout might have an offset with a mean of zero and a standard deviation of 1 mV. On the other hand an opamp with poor layout might have an offset with a mean of 2 mV, but the standard deviation will still be 1 mV. The mean offset is not accounted for by the model so it is important to have a good layout.

The one exception that I know of is having metal over the device - in some process this messes up the anneal and results in a larger spread. There may be other exceptions with the newer processes.

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« Last Edit: Jan 22^nd, 2014, 6:17pm by RobG »

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tulip Community Member Offline Posts: 41	Re: mismatch problem for carefully layouted circuit Reply #4 - Jan 22^nd, 2014, 5:15pm Boe ad Tiger999 have opposite opininons, this reminds me to ask the foundry. RobG, thank you for your careful explaination
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