Hi all,


just wondering, is it practical to have a very small unit capacitance? I am working on a SAR ADC, and while the minimum unit cap in the PDK is about 1.7 fF, it would be better if I could have something even smaller. However, with all the parasitic cap around, I'm wondering if its a bad idea. I've done some simulations, and the parasitic capacitance at the comparator node doesn't seem to affect the SFDR even when its mismatched. However, I haven't simulated any input cap non-linearity. So if the comparator node's capacitance changes with the input signal then I might be in trouble...

Also, I know its possible to add a series cap in the DAC array, but this would degrade the linearity, so I want to avoid that if possible.

Any input is welcome.


thanks,
Aaron

Hi RobG,


thanks for the reply. Yeah I'm aware of splitting the cap DAC, but this degrades the linearity. So I want to avoid it if possible. I ran monte carlo simulations on the cap mismatch alone and it seems good enough. Not sure about noise coupling though...I guess its one more thing I will have to think about.

So do you have an opinion on the minimum capacitance size that should be used?


thanks,
Aaron

Hi loose-electron,


I'll have another look, but I don't think its a bottleneck for my particular implementation. I'm just wondering if there's anything else stopping me from using such a small capacitor. Just for a quick check...

assume 12 bit with 1-V reference, LSB²/12 = 5n V²

kT/C = 5n => C = 0.8pF, so LSB cap = 0.8 pF/2¹² = 0.2 fF.

Have I made a mistake somewhere?


thanks,
Aaron

Hi boe,


thanks for the tip about the charge injection.

I don't really get your point on the kT/C noise though. Are you implying that the LSB cap needs to be large enough so that its kT/C noise is less than the quantization noise? If so, I think I would disagree since in a SAR ADC, the sample and hold is performed on all of the caps together.


Aaron

aaron_do wrote on Jan 28^th, 2014, 4:58pm:
Aaron, you are right regarding kT/C noise - I was a bit too fast on that one.
- B O E

A super small unit cap might be ok for a research project but I would be cautious using one for a production part.

I tried using really small unit caps on a converter a few years ago (noise spec was relaxed) and ended up getting much worse matching than estimated by monte carlo.  If you're using MIMs for best matching you need to be close to where the foundry actually measured data.  Extrapolation is dangerous.  If you're using fringe caps calibration is mandatory since most foundries don't track that.

loose-electron wrote on Jan 30^th, 2014, 10:20am:

Your desire to keep your job  :). I've learned to use my cleverness to decrease risk, not to do something merely because it is more clever than before.  Unless it is a really cool idea of course.

RobG wrote on Jan 30^th, 2014, 10:50am:


This is some of the best advice I've seen in a long time.  I think focusing on risk and being very nervous about being "clever" is a sign of a mature designer.  There's a reason almost all of my Pipelined ADCs use 1.5 bits/stage.