aaron_do
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Hi all,
just wondering, is it practical to have a very small unit capacitance? I am working on a SAR ADC, and while the minimum unit cap in the PDK is about 1.7 fF, it would be better if I could have something even smaller. However, with all the parasitic cap around, I'm wondering if its a bad idea. I've done some simulations, and the parasitic capacitance at the comparator node doesn't seem to affect the SFDR even when its mismatched. However, I haven't simulated any input cap non-linearity. So if the comparator node's capacitance changes with the input signal then I might be in trouble...
Also, I know its possible to add a series cap in the DAC array, but this would degrade the linearity, so I want to avoid that if possible.
Any input is welcome.
thanks, Aaron
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