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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Band gap +LDO transient measurement not in line with simulation Reply #15 - Mar 26^th, 2014, 11:30am Heating? I really doubt it. Look at the time constants of your reference voltage and bandgap. Also, the diodes in the BG often do not have their capacitance in the model, and if you have small bias current the time constants can be really off.
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Lex

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Eindhoven, Holland

Re: Band gap +LDO transient measurement not in line with simulation
Reply #16 - Apr 2^nd, 2014, 1:46am

I share skepticism with Jerry..
I have heard many designers excuse themselves with "thermal response, package stress, substrate noise" and other things that are difficult to check, while for most times the problem turned out to be obvious things like low PSRR, poor settling speed or capacitive coupling.

So how did you do the MC verification? How did you define in simulation whether the BGR is settled? Did you simulate long transients as your measurement result? Are all nodes settled in the simulation?

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RobG

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Bozeman, MT

Re: Band gap +LDO transient measurement not in line with simulation
Reply #17 - Apr 2^nd, 2014, 7:17am

Lex wrote on Apr 2^nd, 2014, 1:46am:

I share skepticism with Jerry..
I have heard many designers excuse themselves with "thermal response, package stress, substrate noise" and other things that are difficult to check, while for most times the problem turned out to be obvious things like low PSRR, poor settling speed or capacitive coupling.

I'll add models to that list of things that get blamed when it is really a something in layout, or a heat gradient Wink

. Whatever you think it is, definitely be skeptical of your hypothesis and verify it thoroughly.

rg

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Band gap +LDO transient measurement not in line with simulation Reply #18 - Apr 2^nd, 2014, 5:14pm http://electronicdesign.com/products/simulation-vs-silicon-avoid-costly-mistakes... give that a read and see if it rings any bells on stuff you left out. high impedance nodes with unaccounted for capacitance attached to it would be my best guess.
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boe Community Fellow Offline Posts: 615	Re: Band gap +LDO transient measurement not in line with simulation Reply #19 - Apr 7^th, 2014, 4:05am Hi, I have already seen a circuit with a start-up time of about 10 seconds [sic!] due to charging of a cap with a MOS in sub-threshold region. - B O E
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