I have a good question: The CMOS die includes a  LDO with band-gap. This CMOS die has only four pads.(VDD, GND EN, OUT). Full simulation across PVT under different extreme conditions have been verified in Cadence simulation which show the LDO output should be competely stable 0.5us after EN is turned on. However, my test results show it take a 400us to settles completely. The Yellow line is EN and another is the LDO output.

This LDO has 20MHz GBW.  

I have checked the power supply line. It is well bypassed by a 10uF capacitor with very small ripple. Does any know why could happen?

Thanks.

-Mikay

Hi Aaron,

The bonding wires are modeled by inductance with 0.5nH/mm. Simulation also shows inductance of ~nH has no effect for the transient since the bandwidth is only 20MHz.(Z=2*PI*20MHz*1nH=0.125ohm).

Where does this large time constant(with ~400us) probably come from?Is there any other possible limiting factor?

Thanks,
-Mikay

aaron_do wrote on Feb 4^th, 2014, 4:49pm:

One thing that could give you that type of response is having a zero that didn't quite cancel a pole (a doublet). The zero gets you that initial fast jump up close to the desired value, but the error in the pole/zero cancellation gives you the final slow settling.

Cancelling a pole with a zero can look great in simulation, but mismatches can give you the result you are seeing. Maybe you can add an external RC network to bring it back in line.

A classic paper was done by Kamath, Meyer, and Grey 40 years ago. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1050527&url=http%3A%2F%2Fi...

Thanks Rob, there may be a in-band doublet in the band gap loop. The loop was not analyzed in detail manually since it's a very complicated architecture. But to ensure a quick loop response, extensive Monte Carlo simulation has been done and all of the simulation results show the band gap starts up very quickly(less than 300ns). Is it possible Monte Carlo simulation could not predict the doublet space(p1-z1)  very accurately and thus the far spaced doublet degrade the speed in the end?

RobG wrote on Feb 6^th, 2014, 9:38am:

Mikey,

the time constant of settling is in the range of typical thermal responses of the active devices.

Does the device model have thermal time constants?

Could you selective switch thermal effects on/off?

BR

Reiner

Mikay,
did you check the load vs. load model in your simulation?
- B O E

how are you measuring startup time.I assume once supply is ramped up and stable you are trying to enable the bandgap. Is the bandgap a very low current structure?Are you adding lot of probe capacitance on the measuring node you are bringing out?

Glad you are zeroing in on the problem - temperature changes seem like a likely suspect given the time constant (good call). Can you vary the load to produce different temperatures and see a difference in the power up transient?

I'm skeptical that a error in the model temp co would cause such a large error - how much of a temperature difference are you predicting as it powers on? What sort of temp co would you need to get your results? Is the change consistent with what you get when you simply change the ambient temperature? Plus why does it come up to the initial value right away only to dip back down? Ask yourself a lot of tough questions before deciding on trim - I would not have guessed that would be the proper solution.

Make sure the bipolars and other matched devices are common centroid - heat gradients will cause an error that can be surprisingly big. You will see different results depending on if you raise the ambient temperature or put a gradient across the chip with power dissipation on one side of the circuit. I'd rule those out before blaming the model.

Also be aware of resistor self heating. Metal line resistance also has a large temp co.