Zorro
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Dear Members,
well it's been a long time since my last post and since I was using verilogams. Now I have a to do a simple model but somehow I cannot figure out what is wrong as the code is not working as I expect it to do. Hopefully you can help me out to find the error.
The basic concept is 1bit dac i.e. the input is a digital signal (1bit) that must be converted into an analog signal.
I want to use "Digital Access on Demand", in more detail "Analog Sensitivity to Digital Events"
As a reference I am using the book "The Designer's Guide to VerilogAMS" by Kenneth S. Kundert", section 3.2.2, page 116, "Analog Sensitivity to Digital Events", Listing 11.
Here is my code:
`include "constants.vams" `include "disciplines.vams" `timescale 1ns/1ps
module dac_1bit_model1 ( out_ana, in_dig); inout out_ana; electrical out_ana; inout in_dig; logic in_dig; real value_ana; analog begin @(posedge in_dig) value_ana = 1.2; @(negedge in_dig) value_ana = 0.0; @(initial_step) value_ana = (in_dig ? 1.2 : 0.0); V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n); end endmodule
Well, for me the code looks ok.
As you can see from pict1 the sensitivity to the events in signal "in_dig" is not working properly because the real variable "value_ana" is corrupt and therefore the transition to V(out_ana) is also corrupt.
I was thinking of possible reasons:
1. I need to include following lines inside the analog block in order to increase the accuracy:
`include "constants.vams" `include "disciplines.vams" `timescale 1ns/1ps
module dac_1bit_model1 ( out_ana, in_dig); inout out_ana; electrical out_ana; inout in_dig; logic in_dig; real value_ana; analog begin @(posedge in_dig) ;
@(negedge in_dig) ; @(posedge in_dig) value_ana = 1.2; @(negedge in_dig) value_ana = 0.0; @(initial_step) value_ana = (in_dig ? 1.2 : 0.0); V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);
end endmodule
the problem is that I have tried this already and I see no difference in the results.
2. I also tried out this code:
`include "constants.vams" `include "disciplines.vams" `timescale 1ns/1ps
module dac_1bit_model1 ( out_ana, in_dig); inout out_ana; electrical out_ana; inout in_dig; logic in_dig; real value_ana; analog begin @(posedge in_dig) $discontinuity(0);
@(negedge in_dig) $discontinuity(0); @(posedge in_dig) value_ana = 1.2; @(negedge in_dig) value_ana = 0.0; @(initial_step) value_ana = (in_dig ? 1.2 : 0.0); V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n); end endmodule
but results are identical.
3. Accuracy Settings, may be I have to change some tool accuracy settings, but I think this is not the problem. So here I have not done any attempt. I am very happy about your suggestions, comments.
Regards! Douglas
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