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ic_engr

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Bandgap Temperature Coefficient susceptibility to packaging stress
Apr 29^th, 2014, 1:14pm

Hello All,

We have a design of 'Banba' Bandgap providing 0.9V. We have temperature trim both PTAT and CTAT added. All simulations show that min and max range of trim provide both PTAT & CTAT to trim each part if needed.

On silicon, both MIN & MAX trims are only providing PTAT and it seems CTAT is not existing. The design is using 1:32 ratio, NPN bipolar.

I have heard from grapevine that packaging stress skews temperature performance of BG circuit and if true has anyone experienced the same. ?
Note that the BG is sitting in the centre of the chip...

The part is now packaged in TQFP and we dont have bare die to test.

Any enlightment...

Regards

ic_engr

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RobG

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #1 - Apr 30^th, 2014, 8:58pm

Plastic packages can mess with bandgap performance. It might even change from one temperature cycle to another. For example, if it is 0.901 at 30C and you bring it up to 125 C, then back to 30C the value now might be 0.904.

It isn't a huge effect (~ 1% IIRC) assuming you common centroided the critical parts to avoid the effects of stress gradients. I'm not sure what you mean by CTAT "not existing," but that makes it sound like a bigger issue than packaging stress.

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: Bandgap Temperature Coefficient susceptibility to packaging stress Reply #2 - May 2^nd, 2014, 7:14am packaging stress is probably not the issue
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ic_engr

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #3 - May 5^th, 2014, 8:10am

RobG,

I did notice that from cycle to cycle is also different.
when I say 'CTAT' I refer to the fact that at max trim I was expecting the voltage to decrease as temperature increases, as per original design simulation. I am not seeing that in Silicon. For both minimum and maximum trim I am seeing voltage increases as temperature increases.

Regards.

ic_engr

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RobG

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #4 - May 5^th, 2014, 8:49am

What is your trim range? (Both voltage and temp co?) Does it match simulations? How does it compare to the cycle to cycle variation?

How are you providing more/less PTAT? The original Banba sums both into a virtual ground.

The current mirror (or the opamp) could have a systematic error that is adding a temp co.

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ic_engr

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #5 - May 6^th, 2014, 2:28pm

RobG,

I should have been mrore clear. I used Banba with curvature compensated circuit. See attached PNG file.

I have separate Voltage trims, and separate Temperature curvature trims. Thus simulation shows for a total trim range for tempco from +133ppm to -100PPM, where as measurement is showing +300PPm to +100PPM

The Voltage trim is done by changing R3
The temperature trim is done by changing R4.

Any ideas ?

ic_engr

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curvature_corrected_001.png

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boe

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #6 - May 7^th, 2014, 4:36am

ic_engr,
you did not say what type of resistors you used. Poly resistors in particular are susceptible to mechanical stress: depending on the assembly process, position on die, etc. assembly may change the resistor values by a few percent.
Of course, it is also possible that the device models of your FAB are not accurate enough.
- B O E

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RobG

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #7 - May 7^th, 2014, 8:00am

Trimming R3 shouldn't change the temp co at all. I'm not sure what effect R4 will have.

It sounds like you have an extra 200ppm/C temp co. This is pretty large. I'm getting rusty, but I think that amounts to an extra 54 mV of PTAT at room to your 0.9 V - a 6% error. That is way more than stress or a modeling error. I'd lean towards a big messup, like the opamp not operating correctly, or big errors from not using dummy devices. Or the startup not shutting entirely off.

Maybe it is an opamp offset? Or resistor mismatch: the ratio of R1 and the left R2 is critical for temp co (the matching of the right R2 isn't as critical). Did you use multiple placements of R1 to create R2?

Who knows... but I doubt if it is packaging. Start checking things like bias current, power supply sensitivity, etc, until you find something funny.

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boe Community Fellow Offline Posts: 615	Re: Bandgap Temperature Coefficient susceptibility to packaging stress Reply #8 - May 7^th, 2014, 8:18am RobG, good points. - B O E
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ic_engr

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #9 - May 7^th, 2014, 8:24am

RobG,

R1 is being trimmed for linear tempco using switches.
Yes, left R2 is a multiple of R1 (unit resistors).
The layout shows Opam diffpair is NOT a common centroid.
I don't believe it is start-up since we raised power supply higher than target and we noted DC value was stable, else I would have expected DC value to change if start-up circuitry was not fully off.

The Resistors are all P+poly HiResistivity.
Q1(N=32) & Q2 are both NPN 5x5.
Q3 (N=15) is NPN 2x2. NOT 5x5.

The only way I can make simulation match the silicon, is if I create a dummy model for Q1 and change the IS (saturation current)i.e. scale IS by a factor of 1.48. But then I am asking myself how could IS of Q1 be different from Q2. In layout Q2 is surrounded by 32 Q1.

Regards
ic_engr

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« Last Edit: May 7^th, 2014, 9:50am by ic_engr »

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boe

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #10 - May 8^th, 2014, 2:02am

ic_engr wrote on May 7^th, 2014, 8:24am:

...
The layout shows Opam diffpair is NOT a common centroid.
...

The Resistors are all P+poly HiResistivity.
Q1(N=32) & Q2 are both NPN 5x5.
Q3 (N=15) is NPN 2x2. NOT 5x5.
...

Did you consider increased opamp offset or larger mismatch between Q1/2 and Q3?
- B O E

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RobG

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #11 - May 9^th, 2014, 6:38am

Looks like you have a mystery to solve. The error is large enough that I'm still thinking big... Can you measure the output current and compare with simulation? (Maybe drive the 0.9V output with 0V and measure the current going into the 0V source?) Maybe low sheet resistors were used!

I've never used that curvature compensation circuit so maybe there is some sensitivity to matching between the two types of bipolars there. Generally bipolar mismatch is negligiable, at least with 5x5 pnps.

You seem to checking the right things with opamp offset, etc... here are a couple more that you might not think of:
32:1 ratio can be on the high side... check the beta vs IC curves and make sure you are on the flat spot with both devices. Another sanity check is to check the delta-Vbe between the 1 and 32x devices vs current and make sure you are in a good flat spot.

Also do a sanity check on base and emitter resistances and make sure your design isn't dependent on them (or beta).

Try to get the measured data for the bipolar and the resistors.

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ic_engr

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #12 - May 13^th, 2014, 7:56am

RobG,

Thanks for the comments, if any of the characteristics e.g. beta vs. IC and delta VBE vs. currents were an issue I should have seen in simulation.
The whole problem is that simulation is not predicting the tempco seen in silicon...

Did I tell you that when I press the TQFP from the top while the part is in socket, at 25C, I do see the Bandgap voltage (900mV)drops down by 1.5mV. So it seems to indicate that there is sensitivity to stress even from outside the package. I wonder how much the die has already been stressed within the package �that MAY have shifted such that at maximum trim I am seeing PTAT instead of CTAT behavior over 0C to 50C.

The only way I can replicate in simulation the PTAT behavior is:
1. if I skew the OPAMP diffpair widths by 15%, but then the DC value goes much higher than that of Silicon..
2. Skew the IS (saturation current) of Q1 (N=32) Bipolar compared to IS (1.4x factor) of Q2 (N=1) in the model file (ofcourse I had to replicate the model and make a dedicated one for Q1 with skewed IS. As I found due to stress the IS of bpolar increases thereby causing tempco shifts. The question is why would stress only affect the Q1 with N-32 and not the N=1 Q1. Is it because there are 32 of Q1 so some those get stressed there by causing increase in IS. ...

We are planning to order some bare die and package those in ceramic and see if the tempco matches simulation....

Would anyone know if I can get a ceramic 32 pin package with 7mmx7mm body same as TQFP to fit in socket ???

Regards

ic_engr,

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RobG

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Re: Bandgap Temperature Coefficient susceptibility to packaging stress
Reply #13 - May 13^th, 2014, 8:53am

ic_engr wrote on May 13^th, 2014, 7:56am:

RobG,

Thanks for the comments, if any of the characteristics e.g. beta vs. IC and delta VBE vs. currents were an issue I should have seen in simulation.
The whole problem is that simulation is not predicting the tempco seen in silicon...

Yup... and if you aren't on the flat part of the curve the bipolar models can be suspect. (Bipolar models are always suspect anyway depending on the person running the curve fitter.) I'm reaching though... you have quite a bit more error than I'd expect from any modeling error or stress, but maybe that curvature compensation circuit adds extra sensitivity.

I had a 10% mismatch in a mirror in 0.18um that didn't use dummy devices.

Good luck and please let us know what you find out.

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ic_engr Senior Member Offline Posts: 135	Re: Bandgap Temperature Coefficient susceptibility to packaging stress Reply #14 - May 13^th, 2014, 2:07pm RobG, Interestingly enough the same topology was designed in a similar process and we were able to get as low as 20ppm with a global trim on all parts. I wonder if process change is part of the problem, 1.8V/3.3V to 1.8V/5.5V Regards ic_engr
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