Hi all,
i have designed a 920 MHz pierce oscillator using 1v vdd transistors included the 45 nm cadence gpdk045 tech. library . During the schematic simulations phase everything works fine. I did the layout and after post layout simulation using the extracted circuit, my circuit wont oscillate. to try to solve this problem, i added the total parasitics (decoupling capacitances only) on each net/node on the extracted circuit to the original schematic. Adjust circuit design to get it oscillating again. I also fingered all wide transistors. I reduced the length of interconnects. i used higher metal layers for interconnects during new layout design. I ran new post layout simulations using the newly extracted circuit. this time i get a tiny damped oscillation. Now my problem is i don't want to continue in this loop for ever as i have limited time before i tape out my design. I'm calling on all experience analog circuit designers to help me. how to i reduce the effects of parasitics? i haven't accounted for resistances and maybe that is the problem am having. how do i added this to my original schematics so that i would have compensated for all parasitics? or is there another and better way to do this in the design?

Thank you for your suggestions. My amplifier has 3 stages. I suppose to increase the gain, i should redesign the aspect ratio of the transitors? I didn't mention that the resonator for the oscillator will be a Mems FBAR and so far I have just been working with it lumped circuit parameters provided by the manufacturer. So basically I don't have that as a degree of freedom. How do u suggest I go on with reducing the impedances?  Sorry for all the questions but this is my first time.

Thank you sir for all your assistance. I have solved my problems! it was just something simple that i was ignoring. Sorry to have bothered you  :) .

For anyone out there who may run into same analog design issues, don't hesitate to contact me.