I use a simple CS-amplifier to verify small-signal model.
L=2.35 nH, and I found peak voltage gain at about 25-GHz,
that means a equivalent shunt capacitor Ceq=17.7f


I did not insert matching network because I think ideal voltage source always gives the right voltage at input node, is that right?
If there is no matching, can AC simulation with ideal source gives me maximum gain this circuit provides?
(If we do matching perfectly, maximum gain can be reached, but I want to evaluate at first)

Now the question is that I don't know how to get 17.7fF from DC operating point.

Maybe Cdg+Cgd+Cdd(all absolute value)=17.6fF is close to the derived value, But how to explain it?
I find a little talks about Cdg Cgd Cdd Cgg......, but I don't know how to use them when calculating.

By the way there is another question.
At low frequency(25kHz), I use ideal resistance 500ohm instead of ideal inductor and find voltage gain can be exactly calculated from Av=gm*(rds//RL).
But at 25-GHz, maximum gain reaches only 10 even if wL=1/wC (means reactance=0). Using DC operating point, it should be Av=gm/gds=11.6, so why it degrades?
Compare to low frequency, how to calculate?
Thanks!

Hi Aron,
I didn't your miller cap calculation, is it from Cgd(1-1/A)? is some thing around 1.08

Thanks,
Raj.

HI, first I have checked the calculation above.
1
The shunt capacitor is miller capacitor in addition of Cds.
Definition of Cds is "capacitive current out of the drain due to a change in source voltage".
but source node is actually short to ground, so why add it?

2
I have proved that maximum voltage gain degrades because some current doesn't flow through M1.

C1=Csg+Cbg=8.75f, C2=Cdg-Covlgd=12.88f, L3=2.35n
Z1=-730.49j, Z2=-496.26j, Z3=367.7j
voltage division = 0.85 and closed to
maximum volatge gain drop expressed as 10.1/11.56=0.874
but notice that
1) I ignored some capacitors are negative(otherwise reactance of them should be positive), does that matter?
2) I didn't take Covlgs into account because I think source node is short to ground, is that right?

3) I also check output noise.
In simulation configuration, I choose outpout as voltage (drain node of M1 as positive and gnd as negative), and input as probe (the ideal volatge source). I run noise and pnoise simulation.

Results are same, that at 25-GHz, output noise equals 164V^2/Hz.
But I found in "noise parameter" output, total noise of M1 is 131.9V^2/Hz, that does not equals 164.

in "noise contribute" output, total noise of M1 is 164V^2, there are some extra items: M1.rg M1.rb M1.rs.

It seems M1.rg M1.rb M1.rs are gate, bulk, source resistance thermal noise, but if it were right, what is /M1 with para rs (value = 7.79e-18), and why para of "M1.rg .rb .rs" are rn? what is rn?
also why M1.rg .rb .rs does not appear in "noise parameter" output?
Thanks for patience!
( I think noise parameter and noise contribute are different, but don't know details, and there are too many cadence help documents I can't find the one I need.)

Thanks.
I will post a result of this problem lter.
I used to deisgn circuits like this (many people around me also),
1) study some qualitative analysis about existent circuits from textbooks, papers or discussion
2) do some coarse calculations of no help
3) iterative design in "try and error" style
and now I regard this so called "intuitive emprical design method" as bottleneck, and how do you design circuits?