In a 3rd Edition of Baker's book, on page 877 he is showing his Fully Differential cascoded amplifier. He is using a 1V short channel process.

According to his table data, his Vds,sat is 50mV for N/Pmos. According to the voltage plots of each node, it looks like all his transistors in saturation.

But obviously, that vdsat is not FIXED in reality with current and all other changing parameters in a transistor.

The thing is, when I tried to simulate that amplifier in an IBM 1.8V process, I find it really hard to get all transistors in saturation.

I am attaching a schematic of that amplifier.



The top PMOS transistor which is highlighed gets out of saturation in a linear region if my bias current is relatively low.

Once I start increasing the bias current, the circled transistors get back to saturation, however, after some time, the underneath highlighted NMOS transitors fall into Triode.

Here is a plot of vds/vdsat for the problematic PMOS and NMOS transitors.


The top diagram is plot of vds and vdsat of NMOS highlighted with line.
The bottom diagram is plot of vds and vdsat for PMOS circled.

As you can see at very low current PMOS is in saturation, but NMOS is not. At higher current PMOS is in saturation, and NMOS falls in linear region.

Also, as you noted, I found some narrow area within which both (and all other transistors in a circuit) are in saturation. However, that region is very narrow with small margin. And it also changes a lot when I change the process corners.

What obvious is the fact that it is kind of impractical to implement such differential amplifiers on a process with 1.8V, yet Baker's book showes it for 1V process..

What I wanted to ask from analog guys who do diff-amps for advanced data converters for CMOS process with 1V or 1.8V, do you ever use such architecture?

Or what other types of architecture you usually use?

Also, I do not want my amp of course to consume a lot of current.

I was curious if you knew some other possible solutions (except that maybe going with multiple stages,....and multiple CMFBs)

Hi,


Quote:


I agree. I think its a bit much to expect a 5-cascode amplifier to work well with a 1-V supply. Even if all the transistors are in saturation at the DC operating point, that will quickly change as soon as the output starts to swing. i.e. the linearity will not be good. Such amplifiers may still be useful in some applications though...

From the research side it seems to me that there are two approaches. First, some people go with I/O devices which allows them to use a higher supply voltage, but incurs a speed penalty. Sometimes they mix the low-voltage devices with the I/O devices to protect the circuit from the high swings while still getting good speed. Those that really want to push the boundaries of the technology, however, use simple structures and then try and solve the poor gain/linearity at the system level using calibration or redundancy or something like that.


regards,
Aaron