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8-bit 50MS/s ADC architecture choice (Read 2759 times)

neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	8-bit 50MS/s ADC architecture choice Jun 14^th, 2014, 10:28am Hi, The requirement is to have 50MS/s data throughput. I have two choices: 1. pipelined ADC 2. 8-way interleaved SAR The technology will be on 0.18um. Which topology will be more efficient in power/area? Regards, Neo
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: 8-bit 50MS/s ADC architecture choice Reply #1 - Jun 14^th, 2014, 6:15pm probably a pipe will get it done in less space - interleaving a pile of converters brings up a bunch of problems beyond just power and area. plenty of papers on the topic out there, time to start doing some research
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neoflash

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Re: 8-bit 50MS/s ADC architecture choice
Reply #2 - Jun 14^th, 2014, 8:48pm

loose-electron wrote on Jun 14^th, 2014, 6:15pm:

probably a pipe will get it done in less space - interleaving a pile of converters brings up a bunch of problems beyond just power and area.

plenty of papers on the topic out there, time to start doing some research

Thank you for your reply. The application seems to sample DC signal and greatly relieves timing mismatch issue.

Given this case, is SAR more attractive?

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: 8-bit 50MS/s ADC architecture choice Reply #3 - Jun 20^th, 2014, 7:48pm 8 interleaved SAR devices is a big headache in alignment and matching
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: 8-bit 50MS/s ADC architecture choice Reply #4 - Jun 20^th, 2014, 10:40pm Hi Neo, Why do you design a 50MS/s ADC to sample DC signal? What's your application? Best Regards, Yawei
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