@aaron,

I didn't
gm ∝ (1+ΔT/1000)

it doesn't imply that there is any feedback... understand this. What I am saying is if temp changes circuit will adjust current to compensate mobility degradation, assume for time being resister is constant.

I strongly believe current mirror also works because of proper -ve feedback at diode connection. Drain potential will be adjusted according to the reference current then matching concept comes. Any how I should thank for your many replies, I guess I should  stop now.

Thanks,
Raj.

Based on quadratic law:
I=4k(V_gs2-V_t)² -> V_gs2=V_t+sqr(I/(4k))
I=k(V_gs1-V_t)² -> V_gs1=V_t+sqr(I/(k))

Filling out
I*R=V_gs1-V_gs2
I*R=1/2*sqr(I/k)
-> I=(4*k*R²)^-1

As for the loopgain, I guess you have to start with the partial derivatives of these equations, since they define the circuits operation. Because of the square root it might be a little tedious to do.

Hi Folks,
I'm not sure how to answer the loop gain question.  If you bias it so that R=1/gm then the output current will be independent of the input current to first order. This is because the Io/Iin transfer function is parabolic as mentioned earlier (see attachment). You don't have to bias it there - but you can. You may be thinking about it too hard.

Anyway, nobody has mentioned it so I'll ramble a little bit. The bottom mirror is an old design called a "Peaking Mirror." I've seen a few articles on them but probably 70s vintage when two transistor circuits were still publishable. It is easier to analyze them using bipolars - but the behavior is the same with MOS.

I've sketched some principles... They may be helpful. Or incredibly boring.  If you were to bias the bootstrapped current source at the peak where gm=1/R it would be insensitive to PMOS mismatch - which actually isn't all that important since we know how to match transistors these days. I could see it having some startup issues if you injected it with high current (on the right side of the peak).

The more useful application is to reduce sensitivity of a current source to Vdd - see the sketch. You can cascade them and get even more power supply rejection... but it is usually just easier/more power efficient to build the old dVgs bootstrapped bias (aka beta multiplier). I never liked the fact that at high currents the output of the peaking mirror goes to zero so I now avoid it in bootstrapped sources, but I have used it to create startup currents with less sensitivity to Vdd.

I suppose you could use the mirror to clean up a noise input current - none of the small signal noise on the input current would pass through.

raja.cedt wrote on Jul 5^th, 2014, 2:35am:


Stability wrt PVT does not imply a negative feedback with a high loop gain. Another way to achieve it is open loop cancellation using matched nonlinearities. e.g. a CS amplifier with a diode connected load of the same type of transistor as the amplifier has a gain independent of PVT. OR a voltage divider with two identical nonlinear devices(e.g. diodes or diode connected transistors).