Hi Members,

I have a question in pipeline ADC's.
I am designing the following bits per stage

4bits per stage first stage followed by 9 1.5 bits/stage.
There is a digital correction so end number of bits is 12Bits.

Since the first sub ADC already resolved the MSB's, does this mean that my first MDAC/gain stage capacitor matching requirement is only 9Bit and not 12 bit?? Since only the residue plot is sent to subsequent stages?

Please enlighten me on this?

Thanks in advance.

Yes I was thinking on the same lines.
The "Residue" needs to be 12 bit, which doesn't depend on capacitor matching. The residue is a sample of vin and DAC out, and at this point the ratio of capacitors still don't come in to picture.
The gain depends on capacitor matching, which requires to be only 9bit.

Let me know if my thinking process is wrong.

thanks carl,

by  "residue" I meant Vin-Vin_digital.
I should have clarified it.

Thanks
Sai

Yes I meant Vin-VdacOutput.
In my head I am trying to imagine in following way:
Step 1) Vin is sampled on a capacitor.
Step 2) Vin is partially digitized by sub ADC, this code is converted in to Analog form [ for example + vref , 0 or -vref].
step 3) subtract Vin - Vdacoutput.
Step 4) send them trough a gain stage. This gain stage depends on capacitor ratios, so matching matters here.

even tough some steps occur simultaneously , the above steps help me understand the concept.

Now with your help and Aaron's I understand it fully.
Thanks

Hi Guys,


first off, carlgrace would know this far better than me....  :P

Anyway I did mention that in a real MDAC you can't look at the operation so simplistically mainly because as carlgrace said the operations happen at once.

I have one question though.

Quote:


the residue of the MDAC is digitized by the rest of the ADC which can be modeled as a lower resolution ADC. If the residue is non-linear, then how can redundancy help to correct it? I thought that redundancy corrects for sub-ADC errors.


thanks,
Aaron

A major part of his question hasn't been answered. Unless you want to calibrate, the first stage capacitor matching does need to be 12 bits. The opamp open loop gain also has to be greater that 2^12 (72 dB). This will ensure that the output of the first MDAC is at least 9 bit accurate.

Also - a minor point, redundancy is used so that the comparators in his 3.5 bit sub-ADC don't have to be 12 bit accurate. Cap mismatch (and low opamp gain) will only cause an error in the gain of the MDAC as Carl pointed out, but that gain error will limit the performance unless it is calibrated out.

aaron_do wrote on Jul 29^th, 2014, 7:45pm:


A bit higher so that isn't the limiting factor, but the loop gain doesn't figure into it (to first order). For example, suppose you had a 72dB open loop gain opamp. This is (barely) good enough for a 12 bit ADC. (Actually I guess it might need to be 78dB to get within 1/2 LSB.) If you wanted to get 1.5 bits in the first stage your gain would be two and your loop gain would be 66dB. This isn't a problem because the output only has to be good to 11 bits. Similarly, if you were doing 3.5 bits in the first stage you'd want a gain of 8, resulting in a loop gain of 54dB. Again, this is ok since the output only has to be accurate to 9 bits. Does that make sense?

In the real world you'd want more margin... I take as much as is easily achievable so I don't have to worry about it over corners. Or whether it is 72dB or 78dB . Also, the input capacitance of the opamp reduces the loop gain.

Snike - Murmann's observations seem consistent with everything said here.