Hi SNIKE,


I think your best bet is to look at the transfer function and also do some system level simulations. Boris Murmann is probably right...


Aaron

Hi Rob,

Thanks for pointing me to Kelly's "JSSC".
I was always checking their ISSCC , where they don't talk much about matching.
I am trying to model the ADC, the problem is the model spits out what equations I plug in.
So hand calculation is as good as modelling.

Now I am clear about the matching part. I am convinced that dnl improves by sqrt(2).

Thanks all for the discussions.

RobG wrote on Jul 30^th, 2014, 8:47am:


The DAC linearity requirement is reduced in a pipelined ADC using a multi-bit first stage because the coarse conversion of the first stage happens BEFORE the residue is generated, it's as simple as that.

If you have a 12-bit converter, and a 3.5-bit first stage, you're converting the 3 MSBs of the your input signal before it even touches the op amp.  The output residue will then be converted by the backend of the ADC, which in this case is a 9-bit converter.

This effect is one of the main reasons you use a multi-bit first stage (the other is power dissipation).  The idea is if you use a multi-bit first stage you can make a 12-bit linear ADC with 10-bit capacitor matching (for instance).
 
BTW I made some lab measurements a few years ago that were consistent with Kelly's paper (assuming the matching data from TSMC was accurate).

Rob is probably right about the kT/C driving the cap size.  That is usually the case in my designs (which is why I like the pure 1.5-bit/stage architecture so much).  Be careful when calculating kT/C requirements for your converter as there are a lot of mistakes in the literature.  

Murmann (he's a helpful guy!) has an excellent tutorial on calculating noise in a switched-cap amplifier the right way:

"Thermal Noise in Track-and-Hold Circuits: Analysis and Simulation Techniques" in IEEE Solid-State Circuits Magazine, June 2012

Sorry *carl

SNIKE wrote on Aug 1^st, 2014, 11:13am:


Yes, listen to Carl on the subject of calibration.  ;) He actually has done a lot of work on the subject.

RobG wrote on Aug 1^st, 2014, 11:16am:


It's time to swallow my pride and agree with Rob now.  

He's right about the matching requirement on the DAC capacitors.  I went through it this weekend and convinced myself the DAC linearity has to be at least as accurate as the current and downstream stages.  So, for a 14-bit ADC, the first-stage DAC has to be 14-bit linear regardless of how many bits you convert.  You were right, Rob.

That said I think the confusion arose because I tend to use 1.5-bit stages whenever possible.  In a 1.5-bit stage, the DAC is inherently linear in a differential sense so the cap matching only affects the closed-loop MDAC gain.  There the requirement DOES relax if you have a multi-bit stage.  So, while a multi-bit stage won't relax your cap matching requirement, it will relax your open-loop opamp gain requirement.

Hope you didn't lose too much sleep, Rob!  ;)