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Jitter Simulation for DLL based Frequency Multiplier (Read 3331 times)
SAAS
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Jitter Simulation for DLL based Frequency Multiplier
Aug 20th, 2014, 12:54am
 
Hi,

I am working on a DLL based frequency multiplier (Cadence 90nm), in which the input frequency is 250MHz and the desired output is 1GHz.
Since I am new to analog designing so I am a little bit confused how to do the jitter simulation. Anybody can please guide.

Thanks in advance

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MAB
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Re: Jitter Simulation for DLL based Frequency Multiplier
Reply #1 - Oct 14th, 2014, 9:16pm
 
Can any body update this, how the jitter simulation is done in the PLL/DLL.
We usually say in PLL high frequency jitter component is removed and limited to LPF BW. Can any body update on jitter analysis.

Thanks,
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Ken Kundert
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Re: Jitter Simulation for DLL based Frequency Multiplier
Reply #2 - Oct 15th, 2014, 11:44pm
 
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