Hi,

I had a question in Verilog AMS setup. Do you know how to use connect modules in a chip which have multiple supply domains. I know one method in which we write using ie card in amsd block in ams control file:

amsd {

… ie vsup=1.8
    ie vsup=3.3 cell=dig_buf  
}

Does anyone know how to do this in cadence gui? Is there any tutorial?

Thanks,
AJ