I wonder how it is possible to construct VGA/PGA that is able to amplify signals which peak-to-peak voltage level is ~2 mV or even lower? What architectures can be used, taking into account that PGA is a part of ASIC. It is not a separate IC packed in a casing.

From my research I know that for PGA following architectures are used:

1. High-gain amplifier with resistor-network feedback

Of course, single input voltage (not differential input signal) architecture as inverting or non-inverting op amp can be used as well.

2. R-r attenuator

3. Differential pair with source degeneration

4. Transconductance ratio

I am aware that there are in-amps on the market that are a separate ICs. These in-amps use a classical 3-op-amp in-amp architecture:

However, they are constructed using super-beta BJTs. For example AD8221.

Its minimum input offset voltage is equal to 25 μV!

However there are ASICs which implement a full system and acquire comparable input sensitivity using PGAs. As an example, see AFE031 of Texas Instruments: http://www.ti.com/lit/ds/symlink/afe031.pdf .

It contains of two PGAs. PGA1 input signal range is 10 Vpp, while input signal range of PGA2 is from GND - 0.1 to 3.3 V + 0.1 V. Receive Sensitivity is equal to: 20 μVRMS, what is a wonderful result! I do not see information about voltage offset value of both PGA, but resolution (receive sensitivity) is remarkable.

What do you think, what architecture of PGAs are used in AFE031? I think that for PGA1 they used op-amp with resistor feedback network, due to the fact that the input signal range is 10 Vpp. It is rather not possible or complicated to have such input signal range using differential pair? If so, what op-amp architectures they used?

Did they use standard CMOS process or they used BJTs?



BTW. Is it possible to insert multiple pictures from my computer? I know I can attach, but I can attach only a single file. I know I can use " ", but it is for web links (right?).

What function are you trying to implement with a PGA?  It is possible to get extremely sensitive PGAs but doing so and maintaining high linearity is difficult as those specs tend to trade off.

It is hard to say what process the part you linked to is realized in, but given the supply rails and the lack of significant digital content besides the SPI I suspect it is BiCMOS.

The methods of programmable gain you showed are all used in practice.  The resistive feedback approach tends to be high noise, and the degenerated diff pair approach tends to have poor linearity.  It's a tough problem.

If you are using an ADC in your ASIC the approach I've seen the most (and used myself) is to use a continuous time preamp (for example method 3 in your post) to get the signal up to a range that is above the noise floor for a Switched-Capacitor PGA.  The switched capacitor PGA has a structure like method 1 in your post but with switched capacitors in place of the resistors.  They can be very accurate but tend to have much higher noise than a continuous-time approach.

b_ganjar1 wrote on Nov 6^th, 2014, 7:32am:


It is a full custom design. It is an ASIC.

carlgrace wrote on Nov 10^th, 2014, 4:00pm:

HomePlug Green PHY

carlgrace wrote on Nov 10^th, 2014, 4:00pm:


Ok, thank you for the information.

loose-electron wrote on Nov 11^th, 2014, 2:21pm:


Bandwidth Fmin-Fmax: 2 MHz - 30 MHz
DC offset: TBD (to be defined) - let's say half the power supply
gain range: largest possible - let's say 0.25 - 128
input amplitude min.: TBD - let's say single mVpp
input amplitude max.: TBD - let's say power supply

Just wanted to get familiar with HomePlug Green PHY and was curious what architectures are used for it, but there is small resources available in the net, thus the question. And yes I know, the chip I indicated, that is AFE031, is for PLC (Power Line Communication).