rosadellavita
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Dear all, I have a question regarding setting the initial voltage for a node in VerilogA, I created a VerilogA capacitor and connected it to my circuit and I want to set the initial voltage of this capacitor depends on the status of another signal, if that signal is 1 V so the initial voltage should be 1, if not the initial voltage should be 0. I know that I can set the ic from the Spectre simulation but I'm looking to control its status through the VerilogA code. I tried to do it through @(initial_step) but it doesn't work! Any idea? Thank you in advance, Rosa
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