Hi

I don't understand your question. The picture shows a rather basic folded cascode OTA with seperate biasing branches for the output for (I assume) common mode regulation.

The MOS will for sure have different W and Ls. Inputs will be rather wide (if offset and speed are not critical even weak inversion), cascodes will also have high gm whereas current sources will be designed as such to have the lowest gds with the allowable output voltage range. The bias voltages for the cascodes should ensure vds of the current sources is above vdsat.

If you have a look at a MOS design book you will for sure find further information on how to design an OTA.

BR

PS:
Beware of the biasing concept: the OTA in the picture only has a gain of gm, not 2*gm, because the left output branch is neither diode connected and fed to the output nor used as an output. So only the current change in M2 affects the output, not the change on M1. A change in M1 will only shift the source voltage of the differential pair and this change goes with gm to the output.

The reference currents are limiting your slew rate so this parameter would be the disgn target.

Please post the total schematic in order to get more help.