Google is your friend. Also it is in many textbooks, and papers in the IEEE JSSC

Research time, and that doesn't mean asking on a web forum.

Let us know when you have some more specific questions.

there is over 1 million Google hits on this topic, many papers in the IEEE JSSC, and pretty much every textbook that is on IC design covers the subject.

if you want useful information you got to ask more specific questions.

Please!

Hi,

There is a whole book out there covering the gm/id appraoch. Basically it means using a SPICE simulator to create characteristic curves of a few basic W/L ratios and using these curves to define the operating point by choosing V* and selecting the desired gm and ft.

I recommend reading through it or searching the cadence sourcelink or this forum. This question is rather frequently asked.

As for the bandgap circuit you showed:
First of all I'm not sure you can call it a real bandgap if there is no bipolar device used. I saw in your schematic that you use a deltaVTH over a resistor and 2*VTH over a resistor to produce what is normally called a PTAT and CTAT current, they are mixed together and create a voltage drop over another resistor. By choosinh the correct factor of the currents you can achieve around 100ppm/K. But thresholds don't match and are much more process dependent. Also they only vary with roughly -1.8mV/K instead pf 2.

The gm/id approach does not really help here to get the DC point correct. Its much more about calculating the derivative of the currents over temperature and mix the with the factors to achieve ideally zero. second order effects like hot carrier or backgate will then lead to the 100ppm/K box model.

The gm/id is then needed if you want to achieve low noise. Rule of thumb: higher current means higher noise. large gm means higher noise. Use long transistors. Use low gm/id and high V* for the current mirrors. VDD headroom and variation is here the limiting parameter. Design the startup circuit with care and simulate both dc swep startup as well as transient fast and transient slow ramp to see startup time. The longer the transistors the longer the time.

The startup circuit you use is basically a very long transistor woth a gate to vdd and a current source from the PTAT generator which is stronger then the resistor when active and an inverter acting as comparator. This is sufficient but you have to ensure that the current from the pmos is everytime larger than the current flowing through the nmos with a vgs of vdd. Both vary with process!

BR

Thanks NOVARIS.

Well for your comment in the circuit that I attached for Bandgap, at first when we our still gathering information and comparing different circuits of a bandgap we consider many factors in choosing that circuit. We found out that as much as possible we need to use or find a bandgap circuit which composed of ALL CMOS. (as you can see in the circuit) At first we didn't plan to find an ALL CMOS bandgap circuit, b'coz, as we observed many researchers in bandgap used bipolar so we decide to used a circuit which have bipolar, but at the end we accidentally found a circuit which have all cmos. And we consider the fact that it is recommended to use all CMOS in a bandgap.

And then we decide to used that circuit but in many papers and information I have now the authors/researchers never explain the importance of a bipolar and the difference of bandgap circuit that having a bipolar compare to bandgap circuit without bipolar. That's why I'm still confused of the importance of the BJT in a bandgap circuit. Do you have any idea about this fact?

Anyway thanks for the reference you gave it to me.

Hi Novaris,

I'm one of the members of comicsanms.
First of all thank you for helping us giving information. It's really a helpful one. I just wanna ask if this schematic can still be used? because the reason why we are having a difficulty in changing our schematic is first, if we used a bipolar transistor we will have a difficulty in layout because bipolar is a complex one. So our adviser said we need to find a all cmos application of this one. Second, because of our tool we are currently using, the electric VLSI and LTspice. Third, if we must change our topology we will have a difficulty in choosing BVR because there are so many papers that they use different topology but we see a paper that implemented an all cmos BVR(just click the file) but they use an opamp instead of a current mirror..any suggestion..thanks a lot you've been a great help to us.

Hi Novaris

This thesis we are currently work on is applying this to 45nm technology and we are currently having a difficult time in sizing the transistors.

Our requirements for this is to supply a constant voltage of 0.65V with a supply voltage of 1V and an accuracy that is depend on how we will get the result. In getting the sizes for the transistor we use the gm/id approach.
We cannot define the temperature coefficient because we are having a difficult time in simulating the circuit with respect to temperature. In our simulation tool(LTspice) which is scad3 ,we are facing problems on getting a SPICE code for temperature variation.

I just wanna ask if how we will use the gm/id because i read some of the gm/id related topics and they have always an input AC signal and a given gain, as for our schematic we don't have set frequency, gain and everything that is related to AC analysis. Because as I saw in our circuit we are working on DC analysis and no AC matter..

Thanks

About the specification and the process technology we were using, we are currently confuse about it. We already define the technology we are currently using(45nm process technology) so no problem about that.

My only concern and confuse right now is our specification. In our specs,
0.65V - output voltage
1V - supply voltage
N/A - accuracy
N/A - TC(temperature coefficient)
required Iptat
required Ictat
Resistors R1 R2 R3

In this specs i just wanna ask if we are the one who will set the value for the required current of PTAT and CTAT and also the resistors.
Im having problems regarding with this one because as you can see we set a 0.65V Vref wherein if we will use ohms law Vref = R3(IR3)
where the current in IR3 is current of PTAT + CTAT where im still also confused.
Because on other papers like this 2 file that I will show to you have different equation in solving it..