sharpmental
Junior Member
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Posts: 14
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Hi Ken,
Yes, i got it now. There is really different direction to think about it.
1st I try to use 2 idt and idtmod. It works but I find when the simulation goes to 5mS or more, some error accumulated. The PWM signal either goes higher and higher or lower and lower. I am not sure if it is the simulator or something else wrong in my system.
Then from your explain, using $abstime should be OK for RF simulation. So I think I can use the operator % to check the time instead of save the "current start time".
Here is my code:
// VerilogA for dc_pwm, veriloga
`include "constants.vams" `include "disciplines.vams" module dc_pwm(VPWM, GND, VCC); output VPWM; electrical VPWM; input GND; electrical GND; input VCC; electrical VCC;
parameter real cycle = 20u; parameter real falltime = 1u; parameter real PWMref = 2.5; parameter integer DEBUG = 0;
real xout; real slope; real wstart; real wtime; real polar;
real PWMvol;
analog begin @(initial_step) begin PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref; wstart = 0; wtime = 0; polar = 1; end
PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;//the high level of PWM singal
wstart = $abstime-($abstime%cycle); //cycle start wtime = $abstime%cycle; //remain time polar = (wtime<(cycle-falltime))?1:-1; // rising or falling part slope = (polar>0)?(PWMvol/(cycle-falltime)):(-PWMvol/falltime); // slope xout = (1+polar)*0.5*slope*($abstime- wstart)+(1-polar)*0.5*(PWMvol + slope*($abstime- wstart - cycle + falltime));
V(VPWM) <+ xout; @(final_step) begin $strobe("Module = %M, slope = %g, wtime = %g, wstart=%g, time is %g", slope, wtime, wstart, $abstime); end end
endmodule
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