vlsi_design wrote on Mar 21st, 2015, 7:40pm:Hi Geoffrey_Coram,
Thank you very much for the reply! I tried to simulate it but I find that Cgate < Cgs + Cgd. Actually it should be Cgate> Cgs + Cgd due to Cgb. I have attached the circuit and curves
Your plot shows Cg (M6, in green) above the other two (Cgs from M9 and Cgd from M12).
Quote:Also why these caps decrease with frequency? Is it due to inversion layer trap phenomenon as explained in device books? But that occurs at 100KHz onward and only when inversion layer is completely isolated.
It's not the inversion layer trap phenomenon. I think it's just a voltage-divider effect with all the different capacitors and conductances (gm, gds -- but maybe also RD,RS, and RG).