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PLL specre simulator settings cause deadzone? (Read 1572 times)
Jeffrey987
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PLL specre simulator settings cause deadzone?
Mar 10th, 2015, 4:54pm
 
Hi,

I'm encountering a weird problem in my 2nd order filter integerN PLL.
Situation: The PLL i'm designing (transistor level) is composed of a PFD, (with buffers) charge pump with opamp as bootstrap, RC C filter and LC tank VCO. A x64 is performed. (Fvco = 2.4GHz)

Depending on the settings of the transient simulation, the PLL shows a limit cycle beahvior that is similar to deadzone. As shown in the figure, the control voltage (AND phase!!!) shows jumps (both Vc and phase jumps as the phase should be the integrated one of Vc).

Setting 1: traponly, 5ps maxstep, conservative  -> limit cycle
Setting 2: traponly, 0.5ps maxstrep , conservative -> no limit cycle.

Transient noise on with fmax=30GHz

I use traponly since it gives faster startup times.

When I remove the VCO and place a linear VCO model in the circuit, the cycle is gone with setting 1. An ideal charge pump does not solve the issue. I checked all PFD signals but they are wide enough.

I checked my PFD + charge pump in open loop simulations but no deadzone is present (sweeping time difference between reference clock and fb clock and measuring the average output current.)

The PLL system is stable, checked in many calculations, model simulations...

Sadly 0.5ps timesteps take a long time to simulate several useconds.

Anyone knows what the origin of this problem is?
numerical issues or circuit issue?

Could the simulation settings cause deadzone somewhere. Since the problem is resolved by removing the VCO, have you ever seen deadzone occuring in a vco?

The image shows the control voltage of the VCO and the phase (time difference from VCOout to and ideal 2.4GHz clock)

Thanks in advance


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pll_001.png
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Frank Wiedmann
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Re: PLL specre simulator settings cause deadzone?
Reply #1 - Mar 11th, 2015, 1:29am
 
This might be trapezoidal ringing, which is a numerical problem (see http://community.cadence.com/cadence_technology_forums/f/38/t/27587). You can check by selecting "Turn On Symbols", then "Show All Points" in the Trace Properties form of ViVA.
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Jeffrey987
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Re: PLL specre simulator settings cause deadzone?
Reply #2 - Mar 11th, 2015, 2:06am
 
I'm talking about the big swings on the control voltage and phase, not the high speed ringing, the fast peaks on the signal are due to the reference spur. The problem is the slow speed (several useconds) cycles. since the reference frequency is 26ns, this is not the same frequency magnitude.
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Frank Wiedmann
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Re: PLL specre simulator settings cause deadzone?
Reply #3 - Mar 11th, 2015, 2:26am
 
Sorry, I did not read your post carefully enough. Some sort of dead zone in a VCO might be caused by injection locking. However, the fact that the effect disappears with a smaller maxstep value seems to indicate a numerical problem.
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Jeffrey987
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Re: PLL specre simulator settings cause deadzone?
Reply #4 - Mar 11th, 2015, 3:20am
 
Any sugestions that I can try? I used other integration methods but the only thing that removes the cycle is reducing the timestep. Is 0.5ps timestep commonly used or is this very low?
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« Last Edit: Mar 11th, 2015, 1:04pm by Jeffrey987 »  
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Jeffrey987
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Re: PLL specre simulator settings cause deadzone?
Reply #5 - Mar 11th, 2015, 1:04pm
 
Can the numerical problems induce deadzone in the VCO because I have never heared aboud deadzone in a VCO... I do not understand this principle of deadzone induction by injection locking?
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Frank Wiedmann
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Re: PLL specre simulator settings cause deadzone?
Reply #6 - Mar 12th, 2015, 2:10am
 
Injection locking means that the frequency of a VCO in a certain range is locked to the frequency (or a multiple or fraction of it) of a different oscillator in the circuit that is somehow coupled to the VCO. In this range, the VCO control voltage has very little influence on the VCO frequency, which could lead to some sort of a dead zone.

Regarding the numerical problems, you should not normally use the maxstep parameter to control the accuracy of a Spectre simulation. The preferred mechanism is the errpreset parameter, in special cases you can also use parameters like reltol, relref, vabstol or iabstol. With these parameters, you only reduce the step size where it is required in order to reach the desired accuracy and not over the entire simulation.
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Jeffrey987
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Re: PLL specre simulator settings cause deadzone?
Reply #7 - Mar 12th, 2015, 4:08am
 
Thanks, I will try this. Have you ever seen a design where the low frequency reference spur on the control voltage causes deadzone in the VCO? The spur on the control voltage is 64x slower than the vco speed. I'm looking weather the ripple is created by a circuit issue or if is is the numerical problem.
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sheldon
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Re: PLL specre simulator settings cause deadzone?
Reply #8 - Mar 12th, 2015, 5:09am
 
Jefferey,

  It is a little difficult to tell from the waveforms, but it looks like
there is a small spike at the reference frequency riding on top
of the control voltage, which would indicate that there is not a
dead zone issue. You did not provide the VTUNE waveforms for
maxstep=0.5ps so it is hard to compare what is happening.
A couple of things to try:
1) turn off transient noise until the behavior is correct
2) When the behavior is correct, only turn on transient noise after
   the PLL has locked
3) Instead of conservative, try moderate with relref=pointlocal
4) Did your models account for the loading of the VCO on the
   loop filter when analyzing stability?
5) Finally with the looser tolerances, it just might take longer to
   settle. Looking at the plot in the lower left, it seems like the
   amplitude of the second peak is a little less than the first.

                                                             Sheldon
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Jeffrey987
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Re: PLL specre simulator settings cause deadzone?
Reply #9 - Mar 12th, 2015, 5:34am
 
Hi Sheldon,

Indeed the reference frequency is on top of the control voltage so the pase detecor and CP do their job. Like Frank suggests, it appears there is deadzone in the VCO. I will simulate the signal again at 0.5ps and plot it. It looks really similar except for the big peaks, the reference clock is stil on top of it but that's due to the PFD/CP principle and is normal.

1) With transient noise disabled, the waveform is still the same (except some small noise).

3) what does this change?

4) yes, the same results are present when an ideal analog buffer (vcvs) is placed between the loop filer and the vco so loading is not the problem. The model is s-domain and thus does not takes spurs into account.

5) no the peaks remain and do not reduce in size

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Jeffrey987
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Re: PLL specre simulator settings cause deadzone?
Reply #10 - Mar 12th, 2015, 7:42am
 
Comparisation
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sheldon
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Re: PLL specre simulator settings cause deadzone?
Reply #11 - Mar 12th, 2015, 5:32pm
 
Jeffrey,

   Strange. Whatever it is, dead zone does not seem to be the issue.
The little spikes at the reference frequency show that your PFD is
working and that the loop is active.

  Again, why don't you try turning off maxstep, using error preset
moderate with relref=pointlocal. This will provide some insight
more insight into the issue.

  Some other questions:
1) Does the PLL frequency change with maxstep? It looks like the
   average values of VTUNE are different for the two simulations?
2) What is the input common mode range of the VCO? Is 0.5V
   volts in the middle of the range or at the lower end of the
   common mode range?
3) Is there a pre-scaler or a divide by 2 to generate quadrature
   at the VCO output?

                                                                    Sheldon
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sheldon
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Re: PLL specre simulator settings cause deadzone?
Reply #12 - Mar 12th, 2015, 6:12pm
 
Jeffrey,

  Another suggestion that addresses the basic issue would be
to go back a few versions and use the Noise Aware PLL flow
to generate a VCO model and use it for transient noise
simulation. There is a meter you can attach to the output
to plot the phase noise.

                                                               Sheldon
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Jeffrey987
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Re: PLL specre simulator settings cause deadzone?
Reply #13 - Mar 13th, 2015, 12:13am
 
Hi Sheldon,

I've seen this presentation online, I seem to do things wrong because this wont work. Is there somewhere a detail description how this flow works?
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Ken Kundert
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Re: PLL specre simulator settings cause deadzone?
Reply #14 - Mar 13th, 2015, 1:31pm
 
You seemed to have dismissed out of hand Frank's initial suggestion that trapezoidal rule ringing might be causing the problem. Did you at least check to see if trapezoidal rule ringing is a problem? I suggest that you should examine the supply currents and make sure they are clean.

It may be that your loop is border-line unstable. Have you performed a stability analysis?

You should also turn off the noise sources until you get this issue resolved.

-Ken
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