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ADC DNL INL simulation using adc_dnl_8bit (Read 2926 times)
kane
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ADC DNL INL simulation using adc_dnl_8bit
Apr 15th, 2015, 8:07pm
 
I am designing SAR ADC and want to use "adc_dnl_8bit" block to get the DNL of the ADC. But I found the amplitude of the "vclk" is too small. 1.  how to solve this problem?  2. where to get the DNL value ?
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weber8722
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Re: ADC DNL INL simulation using adc_dnl_8bit
Reply #1 - Apr 21st, 2015, 11:36pm
 
Hi,

isnt there a parameter to enter the clk amplitude? Use Edit Property, then swtich the cyclic field to "veriloga" to see all parameters.
If this is still a problem use e.g. an vcvs from analogLib as little amplitfier. This is also needed for differential circuits.

Bye Stephan
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