ValarMorghulis
Junior Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/starblue.gif)
Offline
Posts: 10
|
Hi,
I am trying do the noise margin analysis of a dynamic CMOS logic circuit (Domino) which is run by a clock signal. Now, what should be the procedure to do that? I am trying to follow something similar to standard method of measuring noise margin for an inverter using VTC curve.
Thank you for your time and co-operation!
|