After digging deep, I understood the reason.

Now, I have another question related to PFD. The question is "What are the parameters of PLL influenced by PFD ? ".

ex:-
1. Dead zone (decides lower reset length).
2. Increases static phase offset and hence the vco jitter (higher reset length).
3. PLL cannot lock if the reset length is more than half of reference period.

Are there other aspects that needs to be taken care during the design of PFD...?

Thanks,
Lokesh.

My apologies.

In the ideal working case of PFD, reset length is assumed zero. So, if Reference frequency (Fref) is leading the Feedback frequency (Ffb), only U (up pulse is seen) and the D (down pulse remains low). When Fref is lagging Ffb, only D is seen and U remains low. For this case, the S-curve of PFD ( the curve which represents the input phase difference Vs the time averaged differential output [U-D]ave ) is linear between -2Π and +2Π ( as shown in the attaced file). i.e., the range of input phase difference for which the PFD operates correctly is +/- 2Π.

By correct operation, I mean there will not be any missing edges during the comparison.

Now, lets take the case with some reset length ΔR < T ( T = Tref = Tfb ). The maximum input phase differnce for correct PFD operation without missing edges becomes 2Π-ΔR. The other way of seeing this is - if the input phase difference falls between 0 and T-ΔR, PFD operates correctly. But, if the input phase difference falls between T-ΔR and T, alternate edges gets missed. That is, wrong outputs are seen at the PFD output [ This was my Question ]. So, for the PFD to operate correctly, the input phase difference should always be < T-ΔR.

Please let me know if something is not clear (or) correct me if I'm missing something.