Hi all,

If I have designed current mirrors with same ratio but the current that I am mirroring is small that it pushes the transistor close to subthreshold region.

Question is I draw the two mirroring transistors with multiple fingers, each finger will have a very less current, how will it affect?. For example let's say mirror current is 1000nA and there are 10 fingers, each finger will have 100nA. Does this affect the mirroring action?

I know that they are biased closed to the threshold voltage of transistor, the Vth-mismatch will affect it alot, apart from this is there any concern having a transistor operating at 100nA.

Regards
ch

It really depends on the process you are working on. In many CMOS process nodes the leakage current is of the same order as you mention in your question when the channel length is approaching the minimum. In that case you have to make sure that the device size is chosen very carefully.

curious wrote on Aug 6^th, 2015, 12:29pm:

Not really at those current levels - you have half the current but also half the width so it is basically a wash. At higher current levels the gate and source/drain resistances can be an issue.

Quote:

As Tako said, you have to consider leakage. Make the widths as small as possible.

If it is a static mirror then you should be able to take it out of subthreshold by making the device longer. 100nA isn't that low of a current for a properly sized device.

loose-electron wrote on Aug 18^th, 2015, 12:56am:


I see. I was curious, because I have never come across a minimum current remark in foundry documents. So, we should always ask foundry what current range the model support?

I remember that a foundry shares its empirical data in one of its document for a chosen technology. I'll check currents there on Monday.

Very interesting article! Thank You Jerry aka loose-electron!

Tako wrote on Aug 24^th, 2015, 1:26am:



That sounds correct. If the information is uncear contact the foundry and ask them to answer your questions.