Hi I'm trying to simulate the dead-zone present in the phase frequency detector of a PLL.
This is the structure of the PFD I am using.





I have added a delay in the reset path after the NAND gate.

Here are the specs for pulse generators A and B.
Period : 2us
Width: 1us
Rise/Fall : 50ns


UP is QA



If there is a delay of 1us between A and B, QA(UP) is able to capture the phase difference (after I added the delay block of 1us in the reset path)
Waveform:




However, for a smaller delay , say 500ns, and a delay block of 500ns in the reset path, I get this waveform. A 500ns phase difference captured on QA(UP), but I also get another pulse for 500 after that. The same goes for any phase delay less than 1us.
Why do I get this additional pulse on QA(UP)?