The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 23rd, 2019, 11:43am
Pages: 1
Send Topic Print
Generic port width (Read 4142 times)
Sammekevremde
New Member
*
Offline



Posts: 2

Generic port width
Sep 09th, 2015, 2:49am
 
Hi i'm using cadence virtuoso and i'm trying to use a generic to determine the port width in a vhdl entity.

entity Voter is
      generic ( width : integer := 8 );
   Port ( input1 : in  STD_LOGIC_VECTOR (width-1 downto 0);
          input2 : in  STD_LOGIC_VECTOR (width-1 downto 0);
          input3 : in  STD_LOGIC_VECTOR (width-1 downto 0);
          output : out  STD_LOGIC_VECTOR (width-1 downto 0));
end Voter;

when i compile this it gives me the warning.

*WARNING* (DB-270000): dbCreateNet: Input name(or member) : input<width-1:0> has improper bus syntax
*Error* dbCreateTerm: argument #1 should be a database object (type template="dgtxg") - nil
Error failed to create shadow database for (work voter entity).

i've tried to put brackets around the (width-1) which doens't work either.
Back to top
 
 
View Profile   IP Logged
boe
Community Fellow
*****
Offline



Posts: 615

Re: Generic port width
Reply #1 - Sep 10th, 2015, 5:08am
 
Sammekevremde,
AFAIK Cadence Virtuoso (Schematic/Symbol editor) does not support this.
- B O E
Back to top
 
 
View Profile   IP Logged
Sammekevremde
New Member
*
Offline



Posts: 2

Re: Generic port width
Reply #2 - Sep 10th, 2015, 11:49am
 
Thank you Boe.

To bad it isn't supported, would be really nice to be able to use a component multiple times with different parameters.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2019 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.