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May 18th, 2021, 5:04am
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Inquiry about IBM 0.13u process (Read 2113 times)
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Inquiry about IBM 0.13u process
Nov 24th, 2015, 10:46pm
We now have two problems that are related to temperature.

Firstly, according to the BSIM4's model, we should have linear equation between threshold voltage and temperature, while when we simulate the NMOS, it shows totally linear, but in PMOS it shows some non-linearity. I wonder is this temperature non-linearity is caused by which parameter since BSIM4 doesn't include that.

Secondly, when we simulate the output impedance(gds) of a NMOS working in saturation, then sweeping temperature range from 0 C to 120C, we found that gds has some positive slope and negative slope with different Vds. However, in your model, the prt parameter is 0, so we are confused that is there any parameter associated with temperature affects gds? Since we don't know how IBM 0.13um define its BSIM4 model and we don't think it uses the nominal BSIM4 to define the gds model. Thanks!
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Re: Inquiry about IBM 0.13u process
Reply #1 - Nov 30th, 2015, 11:22am
You should really be asking IBM's foundry support directly, not posting here on a public forum.  I don't work for IBM, but I have used BSIM4 a fair amount.

I will note that, while vth0 has a linear tempco as seen in equation (13.1) of BSIM470_Manual.pdf (the latest I have), with KT1, KT1L, KT2 multiplying (T/Tnom-1), there are other terms in Chapter 2 that could have temperature dependence.  T appears in the non-uniform vertical doping, the pocket implant, and short-channel equations.  The complete Vth model is shown in (2.40).

Further, I think the pocket implant could affect gds, as a result of DITS (drain-induced threshold shift).
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