The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Nov 27th, 2020, 6:26pm
Pages: 1
Send Topic Print
1GSa/s ADC: decoupling for power domains isolated by deep n-wells? (Read 9888 times)
spectrallypure
Community Member
***
Offline



Posts: 50

1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Dec 5th, 2015, 8:31pm
 
Hi! I'm having a hard time trying to figure how to implement the on-chip decoupling of the various power domains in my chip. I am implementing a 1GSa/s pipeline ADC in a bulk CMOS process with deep N-well option. The chip floorplan is shown in Fig. 1, and the floorplan of each pipeline stage is shown in Fig. 2. As shown in these figures, I have the following 5 different power domains (please note that besides the logic used for clock signals generation and distribution, I have no other digital circuitry in my chip; all processing/calibration will be done off-chip):

-Vdd_A,Vss_A: the amplifiers power domain,
-Vdd_SW,Vss_SW: the bootstrapped switches power domain,
-Vdd_CMP,Vss_CMP: the comparators power domain,
-Vdd_D,Vss_D: the clock signals generation, buffering and distribution power domain, and
-Vdd_IO,Vss_IO: the output buffers power domain (***I'll make no further reference to this domain since it has already been decided that it will be kept completely isolated from the other 4).

Wherever it happens, each power domain is implemented and contained in a separate deep-N-well region, so in principle all the power domains are isolated to each other (looking back this might not have been the most clever decision, but the core of the ADC has already been laid out like this). Now I need to implement the onchip decoupling of all these power domains, and I'm considering the following 2 options:

OPTION "A": keep all the domains separate and independent.-
A simplified diagram of this option is shown in Fig. 3, and its corresponding decoupling scheme in Fig. 4. As can be seen from these figures, the Vdd and Vss of each domain are decoupled with respect to each other, but no connection/decoupling is implemented between the domains. I believe the pros and cons of this option are:
-Pros: domains completely independent --> maximum isolation
-Cons: domains don't share a common reference --> they could "bounce" relative to each other and induce errors!

OPTION "B": short the grounds of all the power domains.-
A diagram of this option is shown in Fig. 5, and its corresponding decoupling scheme in Fig. 6. Now the domains share a common ground and the Vdd of each domain is decoupled with respect to it.
-Pros: domains share a common reference --> they all would "bounce" together (is this actually a "pro"?)
-Cons: I am shorting the regions that I originally intended to be isolated! (i.e. "local p-sub" regions inf Fig. 5). Even worse, if I also connect the substrate to the common ground (which I most certainly would), then I would be in effect shorting the regions at each side of the deep-N-wells, defying their presence and purpose as "isolation walls" between these regions! (i.e. why would I have put these walls to begin with, if I was going to short electrically the regions they are separating?).

I would really appreciate if anybody could please share any thoughts on this problem. What do you think would be the best option to take? Or maybe non of the above described?

Thanks in advance for any help/advice/comments.

Cheers,

Jorge.









Back to top
 
« Last Edit: Dec 06th, 2015, 12:28am by spectrallypure »  
View Profile   IP Logged
spectrallypure
Community Member
***
Offline



Posts: 50

Re: Onchip decoupling for power domains isolated by deep n-wells?
Reply #1 - Dec 5th, 2015, 8:32pm
 
Fig 1) Chip Floorplan and Fig. 2) Pipeline stage floorplan and power domains
Back to top
 

Fig1_Fig2__small_001.jpg
View Profile   IP Logged
spectrallypure
Community Member
***
Offline



Posts: 50

Re: Onchip decoupling for power domains isolated by deep n-wells?
Reply #2 - Dec 5th, 2015, 8:34pm
 
OPTION "A": Fig. 3) Power domains connection and Fig. 4) Decoupling sheme
Back to top
 

Fig3_Fig4__small.jpg
View Profile   IP Logged
spectrallypure
Community Member
***
Offline



Posts: 50

Re: Onchip decoupling for power domains isolated by deep n-wells?
Reply #3 - Dec 5th, 2015, 8:34pm
 
OPTION "B": Fig. 5) Power domains connection and Fig. 6) Decoupling sheme
Back to top
 

Fig5_Fig6__small.jpg
View Profile   IP Logged
wave
Senior Member
****
Offline



Posts: 117
Silicon Valley
Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #4 - Dec 6th, 2015, 11:37pm
 
spectrallypure wrote on Dec 5th, 2015, 8:31pm:
(looking back this might not have been the most clever decision, but the core of the ADC has already been laid out like this).

I would really appreciate if anybody could please share any thoughts on this problem. What do you think would be the best option to take? Or maybe non of the above described?


Jorge - I'm going to assume this is a research design.
Kudo's for paying attention in the noise/isolation lectures.  You got the theory right, and already seem to see the problem of too much area and complexity.  Not too mention the unrealistic real world of fewer supplies (external regulators, cost, etc.).

DNW isolation is not always even supported in some PDK's so check that first.  Is it too late for a blanket delete of DNW?

If you insist on all these DNW, think about combining some (all?) of the analog supplies (VDD and VSS), in beefy metals.  Maybe even analog and digital together?  

Heck, split these ideas in your tapeout.  You'll get another paper comparing isolations strategies!   Cool

Wave
Back to top
 
 
View Profile   IP Logged
loose-electron
Senior Fellow
******
Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California
Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #5 - Dec 28th, 2015, 4:18pm
 
Deep N Well Isolation is not the answer to the world's problems.

You get capacitive coupling through the PN junction of the DNW and the resistive nature of it allows the coupling to not be killed off by the low impedance bias connection.

Back to top
 
 

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
View Profile WWW   IP Logged
RobG
Community Fellow
*****
Offline



Posts: 569
Bozeman, MT
Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #6 - Dec 30th, 2015, 2:37pm
 
loose-electron wrote on Dec 28th, 2015, 4:18pm:
Deep N Well Isolation is not the answer to the world's problems.

You get capacitive coupling through the PN junction of the DNW and the resistive nature of it allows the coupling to not be killed off by the low impedance bias connection.


I think it was you that told me the deep nwell doesn't buy you much since they are all capacitively coupled. Since then I've heard the same from other sources. That is, the substrate node is an AC short even with NWELL. I think someone told me floating the DNW helped a bit.

The real issue is when currents leave one power domain into another.

There is a paper written on this site about decoupling and bypassing.
Back to top
 
 
View Profile   IP Logged
loose-electron
Senior Fellow
******
Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California
Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #7 - Dec 30th, 2015, 7:12pm
 
Yes that was me. When I was at IBM we had a long "discussion-argument" over the merits of Deep N Well isolation.

At the end of the day we fabbed some test circuits and did some testing.

Helps some, but not a lot to get excited about.
Back to top
 
 

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
View Profile WWW   IP Logged
spectrallypure
Community Member
***
Offline



Posts: 50

Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #8 - Dec 31st, 2015, 12:09pm
 
Thank you all for your replies! (sorry for the delay; the end-of-year rush kept me really busy!).

I have decided to go for Option "B", both for its greater simplicity (too late to delete the Deep-N well layer from all cell layouts --it's hardcoded to the pcell of every MOS device in the PDK), specially speaking about decoupling, and because it is somewhat closer to a more realistic scenario of just having 1 or 2 power domains (although this is a research project, I need to remain as realistic as possible).

After resorting to every source of advice I could think of (including, of course, you guys), the general feeling I got is that this topic is rather badly documented. I suspect that this might have to do with the fact of DNW isolation providing only marginal benefits. If somebody knows of any reference related to these topics (i.e. deep N-well isolation and/or onchip decoupling), I would be really grateful if you could point it out (maybe you, RobG?).

Thanks again for your help, and Happy New Year!!!  :)

Cheers,

Jorge.
Back to top
 
 
View Profile   IP Logged
RobG
Community Fellow
*****
Offline



Posts: 569
Bozeman, MT
Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #9 - Dec 31st, 2015, 1:34pm
 
Here's the paper written by the site owner Ken Kendurt: www.designers-guide.org/design/bypassing.pdf

It's a really complicated topic. Mostly you want to use decoupling to keep the noise currents from creating noise on another block. Be very aware of currents leaving a domain - especially off chip - they have to come back somewhere (Kirchoff's Law) and that will create the noise. Sketch out the circuit blocks and see how the bus drop from one block influences what the other block sees.
Back to top
 
 
View Profile   IP Logged
spectrallypure
Community Member
***
Offline



Posts: 50

Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #10 - Jan 4th, 2016, 7:29am
 
Thanks so much for the link and the comments, RobG; very useful information! Cheesy
I'm getting the feeling that understanding and putting all these concepts together correctly for the case of a complex chip will take me more than a couple of tapeouts to figure out!

Any other tips/references are certainly welcome!

Cheers,

Jorge.
Back to top
 
 
View Profile   IP Logged
loose-electron
Senior Fellow
******
Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California
Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #11 - Jan 10th, 2016, 7:44pm
 
Back to top
 
 

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
View Profile WWW   IP Logged
spectrallypure
Community Member
***
Offline



Posts: 50

Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #12 - Jan 13th, 2016, 2:37am
 
Wow! thank you so much for posting your article, Jerry! I'm going over it right away! Smiley

Cheers,

Jorge.
Back to top
 
 
View Profile   IP Logged
loose-electron
Senior Fellow
******
Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California
Re: 1GSa/s ADC: decoupling for power domains isolated by deep n-wells?
Reply #13 - Jan 16th, 2016, 10:02pm
 
spectrallypure wrote on Jan 13th, 2016, 2:37am:
Wow! thank you so much for posting your article, Jerry! I'm going over it right away! Smiley

Cheers,

Jorge.


No problem, if you got questions LMK, I got a laugh out f digging that out considering how long back I published that.




Back to top
 
 

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2020 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.