Hi Raj.

I am not sure about my answer. However, let me have a guess.

1. Sure the power spectrum density reduces as the spectrum is spreaded. I agree on your calculation. And the shape of spreaded-spectrum depends on you modulation signal shape, too. I recalled that triangular modulation results in a spectrum which has high shoulders. As of the resolution bandwidth, are you sure that spectrum analyzer captures all clock signals if RBW = 1Hz? Its IF frequency bandwidth is too small and I think the clock spectrum is discrete over a 3.3 MHz bandwidth (133.33MHz X 0.025 = 3.33 MHz). I think it is true at least for analog modulation in early stage.

2. I don't remember the modulation frequency for USB 3 or other serial data communication standards. Obviously that your case is for PC mother board. I recall that 133.33 MHz is PCI clock frequency. In that application, the reference clock is a 14.318 MHz crystal outside the chip. If the PLL bandwidth is ~1/20 of reference clock frequency, it is very safe to inject 30kHz analog modulation signal (triangular or other shapes) in the loop filter. That is the reason in the early stage of SSCG used in PC mother board.

I got to know a little bit about SSCG more than 10 years ago. At that time, I did not think about such questions you put forward, especially question 1. So any comments are welcomed.


Best Regards,
Yawei