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ULPAnalog

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Switched capacitor feedback
Apr 08^th, 2016, 8:53pm

Dear experts

I have the following question about the attached circuit. In the context of a continuous time implementation, the shown circuit would have been implemented as a opamp with resistor in feedback, which would mimic a unity gain buffer. Opamp is assumed to be ideal in all aspects (Zin = inf Zout = 0) except for finite DC gain (A). The nominal DC output would then be Vcm*A/(1+A). Now I consider the case where the resistance is replaced with a switched capacitor feedback network, which on an average mimics a resistor.

The question is whether the output voltage will converge to a value close to Vcm in this case or will it keep thrashing between the rails. Also if the limiting characteristics of the amplifier are disregarded for a moment, will the output eventually settle down to a value close to Vcm, given the linear dynamics of the system?

Thanks and regards

PS. I simulated this circuit with Spectre transient analysis and when Cf = Cp and Vcm = Vdd/2 with amplifier exhibiting limiting characteristics (saturating to 0 and Vdd) with A = 1e6, the output oscillates between 0 and Vdd, while a different value for Vcm (2Vdd/3) makes the output settle closer to Vcm.

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scFb.png

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buddypoor Community Fellow Offline Posts: 529 Bremen, Germany	Re: Switched capacitor feedback Reply #1 - Apr 9^th, 2016, 1:55am Question: Why didn`t you realize Cp as a switched capacitor? In your realization it will accumulate charges.
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ULPAnalog Community Member Offline Posts: 97	Re: Switched capacitor feedback Reply #2 - Apr 9^th, 2016, 8:16am Hello Thank you for the reply. Cp modes the parasitics at the inverting terminal. I could reset Cp during phib, but I do not see how that would help. I think it would either still thrash between rails or sit Vdd. Best regards
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RobG

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Re: Switched capacitor feedback
Reply #3 - Apr 11^th, 2016, 9:14am

I think a z-domain analysis will show that it is unstable unless the "round trip" gain for one clock cycle is less than unity (huge Cp or lower A). You could also lower the bandwidth of the amplifier to lower the round trip gain.

The problem is that you are open loop. If you have 10uV of error you will be feeding back -10V on the next clock cycle. If the caps are equal your error will then be about -5V after they are combined, and the next feedback value will be 50e6, and so on. Thus in a real circuit it will simply bang the rails. I'm not sure why it settled with Vcm=2/3Vdd - maybe I'm missing something.

I think it will work if you make Cp a feedback cap. Then you have some continuous time feedback.

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ULPAnalog

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Re: Switched capacitor feedback
Reply #4 - Apr 11^th, 2016, 11:17am

Hi RobG

Thank you for the reply. I agree with you. The reason why I cooked up this circuit was that I have seen some who tend to replace resistors everywhere with SC equivalents and claim correct operation. This was my attempt to verify if that is indeed an universal truth as being claimed by some. Anyway, getting back to the 2/3Vdd thing, I have no idea why it would settle. Here is the output from Spectre transient analysis performed with Cp = Cf and conservative settings for errprst. Interestingly it bangs for a while and settles down in a jiffy.

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tranRespose2_3_Vdd.png

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RobG Community Fellow Offline Posts: 570 Bozeman, MT	Re: Switched capacitor feedback Reply #5 - Apr 11^th, 2016, 3:00pm That simulation is hard to believe. I'd be interested in what happens at the inverting node for both cases. I'm not sure what assumptions need to be made to migrate from a resistor to a switched cap.
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ULPAnalog

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Re: Switched capacitor feedback
Reply #6 - Apr 11^th, 2016, 8:08pm

Hello RobG

I will run a simulation to see how the inverting node looks like as you mentioned. In mean time, I gave a run with Vcm = Vdd/2 but instead of using transient analysis, I used PSS to see how its transient looks like (Ken once mentioned that PSS does more computations than the transient analysis for a given errprst, or atleast that was my understanding). And attached is how the response looks like. Any ideas on what might be going on here?

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pssRespose1_2_Vdd.png

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DanielLam Community Member Offline Posts: 76	Re: Switched capacitor feedback Reply #7 - Apr 12^th, 2016, 1:59am Please post the schematic, and clock signals with inverting node cap node and output node.
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buddypoor Community Fellow Offline Posts: 529 Bremen, Germany	Re: Switched capacitor feedback Reply #8 - Apr 12^th, 2016, 7:34am ULPAnalog wrote on Apr 11^th, 2016, 11:17am: I have seen some who tend to replace resistors everywhere with SC equivalents and claim correct operation. Yes - that`s correct. But where is the S/C equivalent replacing any resistor? The classic intergator in S/C techique always shows two switched capacitors.
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ULPAnalog

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Re: Switched capacitor feedback
Reply #9 - Apr 12^th, 2016, 11:46am

Thank you all for your replies. Attached are the schematics and transient response for the nodes various nodes in the circuit. The opamp is ideal (VCVS with Av = 1e6). I made no changes from yesterday and the result has changed. The output now settles down close to Vcm (I do not really understand why the behavior has changed).

My thoughts are as follows. Transient analysis in spectre by default uses DC op point as initial conditions (as per my understanding). Even with switches being off, there is still a DC feedback path through large off state switch resistances. This is probably why Vin- starts off at Vcm (It did not previously in an earlier simulation and I do not remember skipping dc). Could this explain the output? Also the output thrashes between the rails when dc is skipped. The question is which of these behaviors is correct.

Quote:

But where is the S/C equivalent replacing any resistor?
The classic intergator in S/C techique always shows two switched capacitors.

The SC version is supposed to mimic the resistive feedback version as shown in the attached figure (bottom schematic)

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RFb_v1.png

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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: Switched capacitor feedback Reply #10 - Apr 13^th, 2016, 12:31am This is a circuit that will only work in the ideal environment of the simulator. It is not a viable circuit for the real world. Your feedback loop is always open. In real switched-capacitor circuits, you never open the feedback loop. -Kenav dl -c -f
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RobG

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Re: Switched capacitor feedback
Reply #11 - Apr 13^th, 2016, 7:06am

I played with the circuit last night out of curiosity. If you give it a small amount of DC feedback (say with a 1G ohm resistor) to get the initial condition correct the output will appear to be stable. However, this is an illusion caused by the ideal nature of the simulation, like balancing a latch.

I made the Vcm voltage a pulse and changed it from 0.5V to 0.6V half way through the simulation. This caused it to go back into oscillation.

Given the error at the inverting node from finite opamp gain, I'm surprised the circuit is numerically stable in the simulation environment.

If you want to see something interesting put a 10pF feedback cap in the circuit and keep making it smaller and watch the settling behavior change to unstable.

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ULPAnalog

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Re: Switched capacitor feedback
Reply #12 - Apr 13^th, 2016, 10:42am

Thank you Ken and RobG for your replies and testing out the circuit. It is interesting to know that the circuit broke into oscillations despite having a DC negative feedback (which I thought was the reason for circuit to be unstable) when yanked up. Wondering if is due to circuit being inherently unstable or due to large settling time constants. (This behavior is quite common for capacitively coupled biopotential amplifiers with pseudo resistor feedback. It would take a long time to recover from saturation event).

Also I have not thought about the case of reducing Cf which as RoBG mentioned results in oscillations. Interesting and I need to reason out why.

Ken, in reality an off switch has finite off state resistance and should that not keep the feedback loop closed? Probably the settling is bad, but if clock rates are extremely low, will this be a viable circuit?

buddypoor wrote on Apr 12^th, 2016, 7:34am:

ULPAnalog wrote on Apr 11^th, 2016, 11:17am:

I have seen some who tend to replace resistors everywhere with SC equivalents and claim correct operation.

Yes - that`s correct.

Back to this original question, does it mean, atleast in this particular example, replacing the feedback resistor with a SC equivalent makes no sense?

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RobG

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Re: Switched capacitor feedback
Reply #13 - Apr 13^th, 2016, 12:02pm

I was clocking at 10MHz and my DC feedback was 1G-ohm. At that frequency the resistor provides negligible feedback with 1pF at the input so it is essentially open circuit. If you change the R to 1K the circuit works fine.

I don't know the entire list of differences between a switched cap and a resistor, but one glaring difference in your circuit is the one clock cycle delay that occurs before an output change is fed back to the input. For a system to be stable the amount of feedback has to be less for each time increment, and in your circuit it changes full scale because the opamp is infinite bandwidth.

A resistor should provide feedback quickly compared to the amount the amplifier can change. If you put the same clock delay in series with a feedback resistor it will also oscillate because the output will change too much before the error is fed back to the input. Or you can add another pole in the system that will add a delay.

If I were you, I would write out the difference equations in the form of Vout(n+1) = Vout(n)*K1 + K2 and try to see what is going on mathematically. This is a good circuit to gain insight into stability.

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ULPAnalog

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Re: Switched capacitor feedback
Reply #14 - Apr 13^th, 2016, 12:22pm

RobG wrote on Apr 13^th, 2016, 12:02pm:

I was clocking at 10MHz and my DC feedback was 1G-ohm. At that frequency the resistor provides negligible feedback with 1pF at the input so it is essentially open circuit. If you change the R to 1K the circuit works fine.

I don't know the entire list of differences between a switched cap and a resistor, but one glaring difference in your circuit is the one clock cycle delay that occurs before an output change is fed back to the input. For a system to be stable the amount of feedback has to be less for each time increment, and in your circuit it changes full scale because the opamp is infinite bandwidth.

A resistor should provide feedback quickly compared to the amount the amplifier can change. If you put the same clock delay in series with a feedback resistor it will also oscillate because the output will change too much before the error is fed back to the input. Or you can add another pole in the system that will add a delay.

If I were you, I would write out the difference equations in the form of Vout(n+1) = Vout(n)*K1 + K2 and try to see what is going on mathematically. This is a good circuit to gain insight into stability.

Thank you RobG. It is very helpful. usually I too analyze with difference equations, which showed that circuit should be unstable (with ideal switches), which prompted me to simulate and see what was going on.

Thank you once again. Best regards

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