Hi everybody,

I've been doing a literature search on delay lines for sampling clocks, and there seems to be two main contenders.

1) Current-starved inverters
2) Adding caps onto inverter outputs

Which is more preferable for delay lines for sampling clocks? I am not talking about VCOs where current-starved inverters are prevalent.

I am leaning towards the capacitors as I assume they have less jitter from the supply rails. I am just wondering about other peoples' thoughts.

Thanks,
Daniel Lam