Here is my code :
Code:`include "disciplines.vams"
module test(in, out);
input in;
output out;
voltage out,in;
analog begin
if (V(in)==0)
V(out)<+1;
else
V(out)<+3;
V(out)<+1;
end
endmodule
This is the resulting output
In the first edge:
In=5V and Out=4V
In the second edge:
In=0V and Out=2V instead of 6V.
Since the contribution operator accumulates signal values, shouldn't Out have a potential of 6V? (4V from the previous edge)