lwzunique
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Hi everyone! I came across a weird question about VCO phase noise simulation. The circuit structure is as shown below, VCO+ VCO_BUFFER + DIV_BY_2(CML). when doing pss+pnoise simulation of single VCO or VCO+ VCO BUFFER, the phase noise results is as shown in case 1. VCO output phase noise is -116dBc/Hz@1MHz, and the buffer's output is a little bit worse.
the weird thing is ,when I added div_by_2 block, the phase noise of VCO_OUTPUT AND BUFFER’s output decline rapidly. -93dBc/Hz@1Mhz,-60dBc/Hz@1MHz,repectively. but the div_by_2's output signal's phase noise is -122dBc/Hz@1MHz. [img][/img]
why?
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