JV
New Member
Offline
Posts: 5
Belgium
|
Hi all,
I have some confusions about my simulation setup for the noise of a VCO + buffer circuit, which is used inside a PLL.
The buffer converts the sinusoidal signal from the VCO to rail-to-rail square-wave signals which are driving subsequent frequency dividers. Since the frequency dividers are edge-triggered, I'm using PSS+PNOISE analysis with NoiseType=jitter.
I am using Cadence version IC 6.1.7
- When I tick the NoiseType = jitter box, the PNOISE form talks about "PM jitter for autonomous circuits", shouldn't this be FM jitter since it's an autonomous circuit?
- When the simulation finishes and I go to the "Direct Plot" form, I can choose between Jee, Jc and Jcc jitter. However, I thought that Jee was defined for driven circuits only? What does Jee represent in this case?
Could someone explain please? Many thanks!
|