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 frasheed New Member Offline Posts: 5 Transistor model with variable gate capacitance Oct 29th, 2017, 3:25am   I am modeling a n-type transistor. I already have DC model in verilog-a format. This DC model doesn't have capacitance in it. I am extending it to add gate capacitance. In our process technology gate capacitance is variable (please see the attached image) and I have equation for gate capacitance. From figure, you can see that I have internal gate (ig) terminal which would be the final gate voltage for my transistor. I have a small problem, I only define current through resistor and capacitor using contributions equation: Code:```I(g, ig) <+ V(g, ig)/RG I(ig, d)<+ CGD*ddt(V(ig, d)) I(ig, s)<+ CGS*ddt(V(ig, s)) ```Now If I make an inverter logic using this extended model, if I increase the input voltage (from 0 to VDD) then Output first increase little bit over VDD and then decreases to low voltage (logic 0).I believe the output first increases because of CGD charging and when it is charge , the output gets decreased. Could anyone of you please tell me what is wrong with my modeling approach?.My gate capacitance realization is correct ?P.S: My capacitances values are in nF .Thanks Back to top « Last Edit: Oct 29th, 2017, 7:28am by frasheed »     IP Logged
 Geoffrey_Coram Senior Fellow Offline Posts: 1997 Massachusetts, USA Re: Transistor model with variable gate capacitance Reply #2 - Oct 31st, 2017, 10:28am   frasheed wrote on Oct 29th, 2017, 3:25am: Code:```I(g, ig) <+ V(g, ig)/RG I(ig, d)<+ CGD*ddt(V(ig, d)) I(ig, s)<+ CGS*ddt(V(ig, s)) ```Could anyone of you please tell me what is wrong with my modeling approach? You really should write your model in terms of gate charge. Current is dQ/dt, and for a linear capacitor, dQ/dt = C dV/dt, but for a nonlinear capacitor, this is no longer true. In particular, dC/dt is may be non-zero! Back to top If at first you do succeed, STOP, raise your standards, and stop wasting your time.   IP Logged
 frasheed New Member Offline Posts: 5 Re: Transistor model with variable gate capacitance Reply #3 - Nov 2nd, 2017, 5:06am   Hi Geoffrey_Coram,After changing it to gate charge, I am getting convergence error for inverter logic.Here is my complete code: Code:````include "constants.vams" `include "disciplines.vams" module fet_cap (vd, vg, vs); analog function real sub_threshold; input V0, I0, S, alpha0, lambda, vol_vgs, vol_vds; real V0, I0, S, alpha0, lambda, vol_vgs, vol_vds; begin sub_threshold = I0 * exp(ln(10)/S * (vol_vgs - V0)) * tanh(alpha0 * vol_vds) * (1 + lambda * vol_vds); end endfunction analog function real near_threshold; input a, b, c, d, alpha0, lambda, vol_vgs, vol_vds; real a, b, c, d, alpha0, lambda, vol_vgs, vol_vds; begin near_threshold = (a * pow(vol_vgs, 3) + b * pow(vol_vgs, 2) + c * vol_vgs + d) * (tanh(alpha0 * vol_vds)) * (1 + lambda * vol_vds); end endfunction analog function real gch; input gch0, vth_ch, gamma_ch, vol_vgs; real gch0, vth_ch, gamma_ch, vol_vgs; begin gch = gch0 * pow((vol_vgs - vth_ch), (1 + gamma_ch)); end endfunction analog function real Isat; input beta, vth, gamma, vol_vgs; real beta, vth, gamma, vol_vgs; begin Isat = beta * pow((vol_vgs - vth), (1 + gamma)); end endfunction analog function real alpha; input gch0, vth_ch, gamma_ch, beta, vth, gamma, vol_vgs; real gch0, vth_ch, gamma_ch, beta, vth, gamma, vol_vgs; begin alpha = gch(gch0, vth_ch, gamma_ch, vol_vgs) / Isat(beta, vth, gamma, vol_vgs); end endfunction analog function real above_threshold; input gch0, vth_ch, gamma_ch, beta, vth, gamma, lambda, vol_vgs, vol_vds; real gch0, vth_ch, gamma_ch, beta, vth, gamma, lambda, vol_vgs, vol_vds; begin above_threshold = beta * pow((vol_vgs - vth), (1 + gamma)) * tanh(alpha(gch0, vth_ch, gamma_ch, beta, vth, gamma, vol_vgs) * vol_vds) * (1 + vol_vds * lambda); end endfunction inout vd, vg, vs; electrical vd, vg, vs, ig; branch(vd, vs) vds; branch(ig, vd) vgd; branch(ig, vs) vgs; branch(vg, ig) RG; //Channel geometry parameter W=75u, L=40u; //subthreshold parameter V0 = 0.1740; parameter I0 = 4.1742e-08; parameter S = 0.0297; //near threshold parameter a = 1.2520e-04; parameter b = -4.8064e-05; parameter c = 1.0849e-05; parameter d = -1.0594e-06; parameter alpha0 = 17.1562; //above threshold parameter beta = 3.0211e-05; parameter vth = 0.2429; parameter vth_ch = 0.2430; parameter gamma = 0.1366; parameter gamma_ch = -0.8340; parameter gch0 =  3.8755e-05; parameter lambda = 0.0328; //Limits parameter VGS_epsilon1 = 0.1820; parameter VGS_epsilon2 = 0.3120; real IDS_sub, IDS_near, IDS_above;     /////////////////PARAMETERS FOR CAPACITANCE parameter R = 1; real C, CS, CD, qd, qs; /////////////////////////////PARAMETERS FOR CAPACITANCES END analog begin    //Capacitance I(RG) <+ V(RG)/R; C = 4.29095598e-11 + 5.08332314e-11*tanh(V(vgs)); CS = W*L*C; CD = CS; qs = CS*V(vgs); qd = CD*V(vgd); I(vgs) <+ ddt(qs); I(vgd) <+ ddt(qd); //Capacitance end    if (V(vgs) <= VGS_epsilon1) begin IDS_sub = sub_threshold(V0, I0, S, alpha0, lambda, V(vgs), V(vds)); IDS_near = 0; IDS_above = 0;  end if (V(vgs) > VGS_epsilon1 && V(vgs) < VGS_epsilon2) begin IDS_sub = 0; IDS_near = near_threshold(a, b, c, d, alpha0, lambda, V(vgs), V(vds)); IDS_above = 0; end  if (V(vgs) >= VGS_epsilon2) begin IDS_sub = 0; IDS_near = 0; IDS_above = above_threshold(gch0, vth_ch, gamma_ch, beta, vth, gamma, lambda, V(vds), V(vds)); end   I(vds) <+ W/L * (IDS_sub + IDS_near + IDS_above + 0.3e-9); end endmodule ```Could you please review my code ?. The DC model is from anothe developer I just added capacitance block for transient simulation. Back to top IP Logged
 Geoffrey_Coram Senior Fellow Offline Posts: 1997 Massachusetts, USA Re: Transistor model with variable gate capacitance Reply #4 - Nov 2nd, 2017, 10:06am   You have Code:```C = 4.29095598e-11 + 5.08332314e-11*tanh(V(vgs)); CS = W*L*C; qs = CS*V(vgs); ```Cgs should be the partial derivative of Qs with respect to Vgs, but with what you have written, Code:```Cgs = CS + W*L*V(vgs)*5.08332314e-11*(1-tanh^2(V(vgs))) ``` Back to top If at first you do succeed, STOP, raise your standards, and stop wasting your time.   IP Logged
 Geoffrey_Coram Senior Fellow Offline Posts: 1997 Massachusetts, USA Re: Transistor model with variable gate capacitance Reply #5 - Nov 2nd, 2017, 10:08am   Code:```I(vds) <+ W/L * (IDS_sub + IDS_near + IDS_above + 0.3e-9); ```and what is 0.3e-9 ?? Regardless of the node voltages -- that is, even at zero bias -- you'll get 0.3nA of current. Back to top If at first you do succeed, STOP, raise your standards, and stop wasting your time.   IP Logged
 frasheed New Member Offline Posts: 5 Re: Transistor model with variable gate capacitance Reply #6 - Nov 2nd, 2017, 10:18am   Thank you for your reply.Geoffrey_Coram wrote on Nov 2nd, 2017, 10:06am:You have Code:```C = 4.29095598e-11 + 5.08332314e-11*tanh(V(vgs)); CS = W*L*C; qs = CS*V(vgs); ```Cgs should be the partial derivative of Qs with respect to Vgs, but with what you have written, Code:```Cgs = CS + W*L*V(vgs)*5.08332314e-11*(1-tanh^2(V(vgs))) ``` Regarding your argument that Cgs should be partial derivative w.r.t Vgs. Could you please give me any hints or literature why it should be like this ?. I also found a mistake in my code, CS and CD are not equal, CS and CD values are calculated from different electrodes. This is what it look like now: Code:```vcs = V(vgs); vcd = V(vgd); CS = W*L*(0.4290956 + 0.50833231*tanh(vcs)); CD = W*L*(0.4290956 + 0.50833231*tanh(vcd)); qs = CS*vcs; qd = CD*vcd; I(vgs) <+ ddt(qs); I(vgd) <+ ddt(qd); ```Regarding 0.3e-9, The developer added it for testing purpose. We will remove it. Back to top « Last Edit: Nov 3rd, 2017, 7:09am by frasheed »     IP Logged