Jacki
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Hi,
Normally people in SAR ADC design focus on the mismatch of DAC cap array, and always mention the parasitic capacitance of the top plate in the DAC array just attenuate the input signal, but not add any conversion error. I completely agree. However, this attenuation will reduce the dynamic range of the ADC if we want to measure exactly the input signal voltage. Some applications, i think we are ok with this attenuation, but in some other applications, i think it is important to cance the parasitic capacitance. for example, we want to measure the supply voltage by a 10-bit SAR ADC, if we have 7% parasitic capacitance from the top plate of DAC cap array to the ground, we will reduce the dynamic range by 23dB (actually it is 6-7 bit), it is quite a lot. My question is how to compensate this parasitic capacitance within 0.1%, and make the SAR-ADC to be able to detect the supply votlage in the fully dynamic range? One way I consider is to trim the Vref with the same attenuation, but I don't think it is a good idea because it is hard to do the measurement. another way is we an additional 7% cap of the DAC to VDD, during the bit cycling, we flip the voltage of DAC, and the additional cap will compensate the parasitic cap to the ground. Any other comments?
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