Hello everyone.
I have been looking a little on various websites and on Designer's Guide, but I remain unable to figure out how I deal with this issue.
I am making a set/reset pulse based on an incomming clocked signal (200 kHz at 50% duty cycle). I want to make a give set pulse (pulse width 15 ns) on rising edge and a corresponding reset pulse (pulse width 15 ns) on falling edge.
But I also want a disable input pin, that keeps set low and asserts reset.
My current implementation is shown below, and the basic behaviour works quite well. But I have remained unable to assert reset during disable = high.
Do you guys have any ideas as to how I manage this? Using @cross() in if statements doesn't work naturally, and using if statements in @cross() only checks during a transition.
Code:// VerilogA for set/reset pulse-generator with external reset
`include "constants.vams"
`include "disciplines.vams"
module s144029_SET_RST(Clkin, Disable, RST, SET, Vdd, Vss);
input Clkin, Disable, Vdd, Vss;
output SET, RST;
electrical Clkin, Disable, SET, RST, Vdd, Vss;
parameter real pulsewidth = 15n;
parameter real tt = 10n;
real v_set, v_rst, tend;
analog begin
@(cross(V(Clkin) - 2.5, +1)) begin
v_set = V(Vdd);
tend = $abstime + pulsewidth;
end
@(timer(tend)) v_set = V(Vss);
V(SET) <+ transition(v_set, 0, tt);
@(cross(V(Clkin) - 2.5, -1)) begin
v_rst = V(Vdd);
tend = $abstime + pulsewidth;
end
@(timer(tend)) v_rst = V(Vss);
V(RST) <+ transition(v_rst, 0, tt);
end
endmodule
I hope my question is clear, otherwise I'd love to elaborate.
Best regards Jacob