liletian
Community Member
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Posts: 97
MD
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I have cadence convergence issue.
I am using an verilog A relay
`include "constants.vams" `include "disciplines.vams"
module relay (p, n, ps, ns); parameter real thresh=0; // threshold (V) output p, n; input ps, ns; electrical p, n, ps, ns;
analog begin @(cross( V(ps,ns) - thresh, 0 )) ; if (V(ps,ns) > thresh) V(p,n) <+ 0; else I(p,n) <+ 0; end endmodule
Then the schematic is as following, but it has convergence issue. Can you please help to see if cadence can have a look on the problem?
The square in the schematic is the relay.
the clock waveform is as following:
It keeps reporting the congergence error as below:
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