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Jul 19th, 2019, 3:40pm
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ideal switch convergence problem (Read 1113 times)
liletian
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ideal switch convergence problem
Jul 19th, 2018, 11:36am
 
I have cadence convergence issue.

 I am using an verilog A relay


`include "constants.vams"
`include "disciplines.vams"

module relay (p, n, ps, ns);
   parameter real thresh=0;      // threshold (V)
   output p, n;
   input ps, ns;
   electrical p, n, ps, ns;

   analog begin
     @(cross( V(ps,ns) - thresh, 0 ))
           ;
     if (V(ps,ns) > thresh)
           V(p,n) <+ 0;
     else
           I(p,n) <+ 0;
   end
endmodule


 Then the schematic is as following, but it has convergence issue. Can you please help to see if cadence can have a look on the problem?


 The square in the schematic is the relay.

 the clock waveform is as following:

 It keeps reporting the congergence error as below:

 


 

 
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liletian
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Re: ideal switch convergence problem
Reply #1 - Jul 19th, 2018, 11:37am
 
error message
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liletian
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Re: ideal switch convergence problem
Reply #2 - Jul 19th, 2018, 11:37am
 
waveform
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Ken Kundert
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Re: ideal switch convergence problem
Reply #3 - Jul 19th, 2018, 8:50pm
 
If the switches are open, the capacitor floats.
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liletian
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Re: ideal switch convergence problem
Reply #4 - Jul 19th, 2018, 9:12pm
 
how to solve it?

thanks
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Ken Kundert
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Re: ideal switch convergence problem
Reply #5 - Jul 19th, 2018, 10:18pm
 
resistors to ground.
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