analog_design
Junior Member
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Posts: 23
INDIA
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Hello,
I have question in relation to dummy fill density (tiling).
Does dummy fill parasitic capacitor affect stability of loop e.g. operational amplifier or LDO ?
Has anybody run post-layout simulation on extracted netlist with dummy metal fill ?
I know, It make difference in terms of interconnect delay and timing parameters to digital circuits or long paths ?
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