In the classical type-1 PLL the problem is that the phase correction happens by giving a step increase or decrease in frequency during the static phase offset period. Its like you are trying to maintain a constant distance between your car and a car in front of you. If the other car suddenly goes a little far, you accelerate for a small amount of time and as soon as you are at the distance you stop accelerating.

As you can imagine that would be a very choppy ride.

In terms of PLL, it would have high phase noise.

A better way to implement a type-1 PLL would be sample that static phase error and then distribute it across the entire reference period to align the phase instead of just applying it during the SPO phase. If you can manage to do that, you will get much better PLL performance using a type 1 PLL.