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The Designer's Guide Community Forum › Design › High-Speed I/O Design › jitter tolerance analysis in cadence
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jitter tolerance analysis in cadence (Read 1619 times)
kazkou
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jitter tolerance analysis in cadence
Jan 24th, 2019, 5:50am  
Hi,
I am designing a clock and data recovery using cadence, I want to find the jitter toleance, but I have no ideal how to analysis in cadence, how to do the simulation ? or any guide or reference?
thank you.
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Ken Kundert
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Re: jitter tolerance analysis in cadence
Reply #1 - Jan 25th, 2019, 1:30pm  
http://www.designers-guide.org/Analysis/bang-bang.pdf
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kazkou
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Re: jitter tolerance analysis in cadence
Reply #2 - Jan 26th, 2019, 7:48pm  
Thank you for your reply sir.
Could u tell me where can I find for SONET specification(mask of Jtol and jitter mask etc..)?  I found nothing on internet, only some brief information from wiki.
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