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VCO VerilogA hidden state (Read 258 times)
Marios
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VCO VerilogA hidden state
Apr 02nd, 2019, 7:06am
 
Dear all,

I am using the VerilogA VCO code without jitter provided here : https://designers-guide.org/verilog-ams/functional-blocks/vco/vco.va

I am trying to run a PSS analysis but the analysis won't converge whenever this VCO is added to the testbench (just sitting there with its input fixed at 0). I guess that this could be due to the hidden state (variable integer n in the code).

Any ideas how to overcome this?
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Ken Kundert
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Re: VCO VerilogA hidden state
Reply #1 - Apr 2nd, 2019, 5:45pm
 
Generally the simulator will warn you about hidden state.  Your description of what is going wrong is not very helpful (the VCO does not control its input, so it is not obvious from your description why the input should not just sit with its input at 0V). You also do not say which VCO you are using.

When using SpectreRF, you should be using a model without jitter.

You can modify vco1 to eliminate the hidden state by converting the output from a square wave to a sine wave:

Code:
analog begin
    // compute the freq from the input voltage
    freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

    // bound the frequency (this is optional)
    if (freq > fmax) freq = fmax;
    if (freq < fmin) freq = fmin;

    // bound the time step to assure no cycles are skipped
    $bound_step(0.2/freq);

    // phase is the integral of the freq modulo 2pi
    phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

    // generate the output
    V(out) <+ ampl*cos(phase);
end 



-Ken
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Marios
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Re: VCO VerilogA hidden state
Reply #2 - Apr 3rd, 2019, 4:08am
 
The VCO code follows:


////////////////////////////////////////////////////////////////////////////////
////
`include "disciplines.vams"
`include "constants.vams"

//
// Voltage controlled oscillator with no jitter
//

//(* ignore_hidden_state *)

module vco1 (out, in);

input in; voltage in;                        // input terminal
output out; voltage out;                  // output terminal
parameter real vmin=0;                        // input voltage that corresponds to minimum output frequency
parameter real vmax=vmin+1 from (vmin:inf);      // input voltage that corresponds to maximum output frequency
parameter real fmin=1 from (0:inf);            // minimum output frequency
parameter real fmax=2*fmin from (fmin:inf);      // maximum output frequency
parameter real tt=0.01/fmax from (0:inf);      // output transition time
parameter real ttol=1u/fmax from (0:1/fmax);      // time tolerance
parameter real ampl=0.5 from (0:inf);
real freq, phase;
integer n;

analog begin
   // compute the freq from the input voltage
   freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

   // bound the frequency (this is optional)
   if (freq > fmax) freq = fmax;
   if (freq < fmin) freq = fmin;

   // bound the time step to assure no cycles are skipped
   $bound_step(0.2/freq);

   // phase is the integral of the freq modulo 2pi
   phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

   // generate the output
   V(out) <+ ampl*cos(phase);
end

endmodule
////////////////////////////////////////////////////////////////////////////////
////

I am modelling a TYPE I 2nd order pll consisting of a PFD, a filter and the vco above. Filter is 1st order implemented using analogLib components. PFD is a real design.

The PLL will lock when running transient and seems to operate as expected. However the PSS does not converge. The following issues are reported in the simulation output log.


    pss: time = 50.98 ns    (97.8 %), step = 3.333 ps     (333 m%)
Conv norm = 143e+03, max dV(I11:idt0) = 19.5231 kV, took 3.52 s.


Notice from spectre during periodic steady state analysis `pss'.
   388 warnings suppressed.
       Further occurrences of this notice will be suppressed.


==============================
`pss': time = (50 ns -> 51 ns)
==============================

Error found by spectre at time = 50.064 ns during periodic steady state analysis `pss'.
   ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified.  Last acceptable solution computed at 50 ns.

The values for those nodes that did not converge on the last Newton iteration are given below.  The manner in which the convergence criteria were not satisfied is also given.
           Failed test: | Value | > RelTol*Ref + AbsTol

Top 10 Residue too large Convergence failure:
   V(I21.I12.Q81<0>:dt) = 22.752 MV, previously 22.752 MV.
       residue too large: | 5.48152e+21 A | > 5.48152e+18 A + 1 pA
   V(I21.I12.Q90<7>:dt) = 1.32158 MV, previously 1.32158 MV.
       residue too large: | 3.81769e+21 A | > 3.81769e+18 A + 1 pA
   V(I21.I12.Q90<6>:dt) = 1.32115 MV, previously 1.32115 MV.
       residue too large: | 3.81772e+21 A | > 3.81772e+18 A + 1 pA
   V(I21.I12.Q90<5>:dt) = 1.32131 MV, previously 1.32131 MV.
       residue too large: | 3.81744e+21 A | > 3.81744e+18 A + 1 pA
   V(I21.I12.Q90<4>:dt) = 1.32116 MV, previously 1.32116 MV.
       residue too large: | 3.81765e+21 A | > 3.81765e+18 A + 1 pA
   V(I21.I12.Q90<3>:dt) = 1.32141 MV, previously 1.32141 MV.
       residue too large: | 3.81757e+21 A | > 3.81757e+18 A + 1 pA
   V(I21.I12.Q90<2>:dt) = 1.32157 MV, previously 1.32157 MV.
       residue too large: | 3.81767e+21 A | > 3.81767e+18 A + 1 pA
   V(I21.I12.Q90<1>:dt) = 1.32112 MV, previously 1.32112 MV.
       residue too large: | 3.81755e+21 A | > 3.81755e+18 A + 1 pA
   V(I21.I13.Q77.Q1<3>:dt) = -74.0367 MV, previously -74.0367 MV.
       residue too large: | 11.8857e+21 A | > 11.8857e+18 A + 1 pA
   V(I21.I13.Q77.Q1<2>:dt) = -74.0341 MV, previously -74.0341 MV.
       residue too large: | 11.8858e+21 A | > 11.8858e+18 A + 1 pA


The values for those nodes that did not converge on the last Newton iteration are given below.  The manner in which the convergence criteria were not satisfied is also given.
           Failed test: | Value | > RelTol*Ref + AbsTol

Any input as to what the issue might be is much appreciated.

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« Last Edit: Apr 3rd, 2019, 8:13am by Marios »  
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Ken Kundert
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Re: VCO VerilogA hidden state
Reply #3 - Apr 4th, 2019, 2:08pm
 
I don't think this is a hidden state issue. Try the normal convergence strategies. Did you set tstab long enough so that PLL has gone into lock?

-Ken
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Re: VCO VerilogA hidden state
Reply #4 - Apr 5th, 2019, 12:19am
 
Yes I have. The PSS itself detects the steady state (analysis output log) but cannot proceed beyond the point in time that the PLL settles.

If I select detect steady state, it will detect it at 30ns but wont get passed that point and will fail without convergence.

If I set tstab = 1us, it will fail at 1us without convergence!
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Re: VCO VerilogA hidden state
Reply #5 - Apr 6th, 2019, 12:23am
 
The first thing to check is where you are actually reaching steady state.  The way to do that is turn on strobing with the strobe period being the period of the PLL in lock. Then examine the waveforms and see whether they become constant valued.  When in steady state, all the strobed waverforms should be constant.

Specifically I recommend plotting the strobed supply current. If there is any non-periodic behavior in your circuit should show up the the supply current.

-Ken
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