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Apr 20th, 2019, 7:31am
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Verilog-A Convergence issues with diodes and big netlists (Read 46 times)
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Verilog-A Convergence issues with diodes and big netlists
Apr 06th, 2019, 1:48pm
I would like to open a general discussion topic on issues I found while developing a model for multi-collector bipolar transistors in HV CMOS technologies, hoping some expert can give to me and generally to compact-model developers some hints.

There are many hints already published regarding how to write compact models that I tried to follow them up to my best, however few limitation points come from the available simulators (my experience is reduced only to one simulator) that generate always convergence issues.

1. We have functions like sqrt, pow and log that by definition have derivative discontinuity. Could I conclude that those built-in functions should be never used and we have to write our smooth functions with good derivative behaviour?

2. If we have a simple resistor parameter in the model that depending on the model card can be very high or very small, which is the best way of implementing it? With an alternate base if()...I()<+ V()/R ...else V() <+ I()*R or there are better ways?

3. limexp, I noticed it is implemented as an hard clipping of the exponential for very high value, which actually introduces a discontinuity. I never found any improvement in using it but neither any problem. What I think will be more useful for a diode model for example is the $limit function of verilog-A manual. Someone knows one simulator supporting this function?

4. gmin and gdev. Someone can explain to me the difference? Do you know when the simulator use the gdev homotopy?

5. Now a diode model is simple, it will converge. My problem is that I have a netlist of  more than 5000 (!) of those verilog-A diodes connected together and there the problems start. With this big netlist the dc convergence is difficult because the diodes can be forward (my goal all over is to model BJT..) or reverse biased and I did not find an easy way to help the simulator to start from some potential nodes by propagating the boundary condition from the "pin-out" of the testbench. Any hint?

6. If I have a huge netlist and for some reason some of the verilogA device terminals are left floating the convergence is even worst. Is there any option in verilogA code or in the netlister to mitigate this problem (basically a recognition of a floating terminal)?

7. When talking about thousands of instances of a verilogA code, it is not more efficient for example to write the model in plain C? Someone has experience with the CMI interface of Cadence and how to have access to it?

Thank you for any support.

Best regards,
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Re: Verilog-A Convergence issues with diodes and big netlists
Reply #1 - Apr 8th, 2019, 8:42am
You have a lot of questions; let me see if I can answer a few of them.

1. You do need to be careful with your use of sqrt, pow, log. However, "never" is too strict: you can certainly use them when the arguments are all constant (or at least not bias-dependent). You should be able to use sqrt as long as you are sure the argument is always positive -- if it's negative, the result is complex (which makes no sense), but also watch out for the argument being zero, because the derivative is not defined there.

2. This may depend on the simulator; I think I used one a while ago that would automatically reformulate V <+ ... to I <+ ... because it thought that was a better formulation. You may want to consider whether you can simply eliminate the resistor if it's too small.

3. limexp should not be implemented as a "hard clipping." If your simulator is doing this, you may want to write your own function to linearize the exponential at a breakpoint.

7. I got involved in Verilog-A years ago because someone told me that CMI was too hard to just use. And Verilog-A is pretty good, if you have a decent compiler (you're not looking to go to assembly language because of concerns about the C compiler - a good VA compiler shouldn't have issues with 000s of instances). Some simulators do have a special optimization that they can perform on compact models (like diodes or BJTs) written in Verilog-A; in particular, this can help with the memory usage if your model has a lot of parameters. This is simulator-specific, so you may need to as the vendor about whether .model cards are supported for Verilog-A instances.
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