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May 25th, 2019, 6:46pm
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DAC Jitter Modeling for CTSD Modulator (Read 70 times)
Ramy_Rady
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DAC Jitter Modeling for CTSD Modulator
Apr 19th, 2019, 8:22pm
 
Hello,

I was implementing a 5 bit DAC to be used in a CT sigma delta modulator. I would like to model the error due to clk Jitter at the output of the DAC in VerilogA. Any Ideas?
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