Tesla
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@Geoffrey_Coram You are correct about both points, especially the 2nd one. I need to modify the code to fix this potential bug.
@Ken Kundert My apology for not describing the problem clear enough. I figured out yesterday. I made 2 mistakes, if this is useful to anyone: 1. In the port, I incorrectly specified PAC magnitude instead of AC magnitude to be 1. This means,that there is no signal stimulation for AC. That caused the capacitance measurement to give unreasonable value. 2. Because the capacitance measurement gave incorrect value, I suspected that it must be the decoder is not giving correct control signal. And when I probe mod_out in the direct plot form, choosing ac analysis, I saw every wire is 0V, while I expected some of them to be vdd. However, my expectation was wrong because there is no ac excitation for the veriloga block, therefore the output is 0V for ac analysis. After I corrected the signal profile at port, the capacitance value is what I expected. So the incorrect behavior I observed was not caused by the veriloga block itself.
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