The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Sep 17th, 2019, 3:43pm
Pages: 1
Send Topic Print
Veriloga assignment not affecting ac simulation (Read 137 times)
Tesla
New Member
*
Offline



Posts: 4

Veriloga assignment not affecting ac simulation
Sep 06th, 2019, 8:40am
 
I wrote a decoder to translate an binary code to the control signal in circuit, in a lookup table manner. For example, 0001 at input is mapped to 00101 at output.
The loading of this decoder can be a switchable capacitor bank. And ac simulation would be run to test what is the capacitance versus the code.

However, I found that the output of this veriloga block is not responsive to its input code in ac simulation, even if the output of this veriloga code is used to control the control signal of the capacitor bank, i.e. I only need the ac behavior of the capacitor bank, not the veriloga block itself. However, the veriloga block not generating the correct voltage, or any voltage at all, sets the capacitor bank at a wrong value.

However, the veriloga block behavior is correct in DC and TRAN analysis.

I wonder whether someone knows whether I should write the code in a different manner.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2218
Silicon Valley
Re: Veriloga assignment not affecting ac simulation
Reply #1 - Sep 6th, 2019, 1:17pm
 
I think you forgot to add your code.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
Tesla
New Member
*
Offline



Posts: 4

Re: Veriloga assignment not affecting ac simulation
Reply #2 - Sep 6th, 2019, 3:02pm
 
I dont have the file at hand now, but below is the "pseudo" code.

module deoder (vdd, gnd mod_in[2:0], mod_out[1:0])
input vdd, gnd; electrical vdd, gnd;
input [2:0] mod_in; electrical [2:0] mod_in;
output [1:0] mod_out; electrical [1:0] mod_out;
integer mod;
analog begin
@(initial_step) begin
mod = (V(mod_in[0])>0? 1:0) + 2*(V(mod_in[1])>0? 1:0)+4*(V(mod_in[1])>0? 1:0)
end
if ( mod >0 && mod<=2) begin
    V(mod_out[1])<+V(vdd);
    V(mod_out[0])<+V(vdd);
end
else if (mod >2 && mod <=4) begin
    V(mod_out[1])<+V(gnd);
    V(mod_out[0])<+V(vdd);
end
else if (mod >4 && mod <=8) begin
    V(mod_out[1])<+V(gnd);
    V(mod_out[0])<+V(gnd);
end
end
endmodule
Back to top
 
« Last Edit: Sep 7th, 2019, 12:47am by Tesla »  
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2218
Silicon Valley
Re: Veriloga assignment not affecting ac simulation
Reply #3 - Sep 7th, 2019, 4:13pm
 
How are you performing AC simulation with this model. How are you stimulating the circuit. How are you measuring a response?

-Ken
Back to top
 
 
View Profile WWW   IP Logged
Tesla
New Member
*
Offline



Posts: 4

Re: Veriloga assignment not affecting ac simulation
Reply #4 - Sep 9th, 2019, 12:46am
 
I connect the output mod_out[1:0] to the gates of transistors. And each transistor is in series with a capacitor, i.e. the transistor works as a switch.
Each branch is connected to, say left node a and right node b. And there are several branches in total. So that the capacitance value between node a and b should be responsive to mod_out[1:0]
How to excite the circuit: I place a port between node a and b, with an AC magnitude of 1.
How I measure the response:I measure the AC current and voltage at node a and b.
Back to top
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1975
Massachusetts, USA
Re: Veriloga assignment not affecting ac simulation
Reply #5 - Sep 9th, 2019, 10:53am
 
I think the second reference to mod_in[1] should be mod_in[2]:

mod = (V(mod_in[0])>0? 1:0) + 2*(V(mod_in[1])>0? 1:0)+4*(V(mod_in[1])>0? 1:0)

And your output lines in your pseudo-code don't seem to handle mod=0 (if all the inputs are 0).
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2218
Silicon Valley
Re: Veriloga assignment not affecting ac simulation
Reply #6 - Sep 9th, 2019, 8:34pm
 
I cannot parse your description. If you want help, you need to give specifics. Meaning you have to give the actual model you are using and you have to give a schematic. Otherwise you are just wasting everyone's time.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
Tesla
New Member
*
Offline



Posts: 4

Re: Veriloga assignment not affecting ac simulation
Reply #7 - Sep 10th, 2019, 12:40am
 
@Geoffrey_Coram You are correct about both points, especially the 2nd one. I need to modify the code to fix this potential bug.

@Ken Kundert My apology for not describing the problem clear enough. I figured out yesterday. I made 2 mistakes, if this is useful to anyone:
1. In the port, I incorrectly specified PAC magnitude instead of AC magnitude to be 1. This means,that there is no signal stimulation for AC. That caused the capacitance measurement to give unreasonable value.
2. Because the capacitance measurement gave incorrect value, I suspected that it must be the decoder is not giving correct control signal. And when I probe mod_out in the direct plot form, choosing ac analysis, I saw every wire is 0V, while I expected some of them to be vdd. However, my expectation was wrong because there is no ac excitation for the veriloga block, therefore the output is 0V for ac analysis.
After I corrected the signal profile at port, the capacitance value is what I expected. So the incorrect behavior I observed was not caused by the veriloga block itself.
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1975
Massachusetts, USA
Re: Veriloga assignment not affecting ac simulation
Reply #8 - Sep 11th, 2019, 10:28am
 
That sort of proves Ken's point: you need to give specifics - the actual model and netlist, so we would have a chance of noticing the "pac" instead of "ac".
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2019 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.